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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b55138043b6sm8998663a12.26.2025.09.21.23.58.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 21 Sep 2025 23:58:25 -0700 (PDT) Message-ID: <14cdf3a4-714c-4136-8c1d-99392e7911f5@oss.qualcomm.com> Date: Mon, 22 Sep 2025 14:58:17 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 12/14] phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250919-add-displayport-support-for-qcs615-platform-v5-0-eae6681f4002@oss.qualcomm.com> <20250919-add-displayport-support-for-qcs615-platform-v5-12-eae6681f4002@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 65KxqQt4Zx4JplAYFuxyDbVDYMG-qaXc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAxOCBTYWx0ZWRfXyH+uGBOm+2x/ 0vgCpT3hzDW4w5v40TDiNzpcVcF56Tk2fbe7jWiC0qtl5dv33FKt4ddi+SaFYWQV0TFjSirahEe 8UCTOkmeMKbxdlm9NyBUCeCNLpSFOYnbxMRYGUTBGOAYn2kYXLFR+aQFVrEha3Y0TYGauoaeHOZ +b/cszB1KYD6CeihnwMJgVm+AZjRDjkCerqpLTsoFnI0mpFRFl+HFcSv46IIjXASfIaeJlsvW6v YoKSBni5tMbzPwP1agFtTWGxObLk+xEnaYjG7Re3UffQf5YS5VOJYQi3fcKwUGGn/nypyJPuLNT JHPkfdDmjU0EBw4OzFRYd+AFSAVlJeO1wlQgIRD0hde3u7tfszlJAdbiVntn5K79OK1lD8oi9LD HGIWCAzD X-Proofpoint-ORIG-GUID: 65KxqQt4Zx4JplAYFuxyDbVDYMG-qaXc X-Authority-Analysis: v=2.4 cv=Dp1W+H/+ c=1 sm=1 tr=0 ts=68d0f393 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=JsSO4BFUhKJy4KAi8vwA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-22_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200018 On 9/20/2025 2:41 AM, Dmitry Baryshkov wrote: > On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote: >> Add QCS615-specific configuration for USB/DP PHY, including DP init >> routines, voltage swing tables, and platform data. Add compatible >> "qcs615-qmp-usb3-dp-phy". >> >> Signed-off-by: Xiangxu Yin >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 395 +++++++++++++++++++++++++++++++ >> 1 file changed, 395 insertions(+) >> >> + >> + writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >> + writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); >> + writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); >> + writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); >> + writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); >> + writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); > Are you sure that these don't need to be adjusted based on > qmp->orientation or selected lanes count? > > In fact... I don't see orientation handling for DP at all. Don't we need > it? Thanks for the review. I agree with your reasoning and compared talos 14nm HPG with hana/kona 7nm PHY HPG; the 7nm COMBO PHY series has orientation/lane-count dependent configs, but the 14nm PHY series does not. On QCS615 (talos), the TX_* registers you pointed to are programmed with constant values regardless of orientation or lane count. This has been confirmed from both the HPG and the downstream reference driver. For orientation, from reference the only difference is DP_PHY_MODE, which is set by qmp_usbc_configure_dp_mode(). The DP PHY does have an SW_PORTSELECT-related register, but due to talos lane mapping from the DP controller to the PHY not being the standard <0 1 2 3> sequence, it cannot reliably handle orientation flip. Also, QCS615 is a fixed- orientation platform (not DP-over-TypeC), so there is no validated hardware path for orientation flip on this platform. > >> + >> + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); >> + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); >> + >> + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, >> + status, >> + ((status & BIT(1)) > 0), >> + 500, >> + 10000)){ >> + dev_err(qmp->dev, "PHY_READY not ready\n"); >> + return -ETIMEDOUT; >> + } >> + >> + return 0; >> +} >> +