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Mon, 02 Nov 2026 05:03:09 -0800 (PST) Received: from [192.168.226.248] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5bfe072d19csm1698389e87.40.2026.11.02.05.03.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 05:03:08 -0800 (PST) Message-ID: <14d63775-3024-47fa-a495-60351c31e6eb@oss.qualcomm.com> Date: Mon, 2 Nov 2026 14:03:03 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 09/14] drm/msm: initialize LPAC ring To: Anna Maniscalco , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org References: <20261029-descriptive-name-lpac-upstream-v2-0-a21a5c850961@gmail.com> <20261029-descriptive-name-lpac-upstream-v2-9-a21a5c850961@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261029-descriptive-name-lpac-upstream-v2-9-a21a5c850961@gmail.com> Content-Type: text/plain; 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The series enables LPAC on gen70900 (Adreno 750), which already has ADRENO_QUIRK_IFPC. When LPAC is active, patch 09 programs several GX registers in hw_init(), but adds only CP_LPAC_PROTECT_CNTL to the A750 IFPC restore list. The missing registers are: - UCHE_DEBUG_CNTL_1 (bit 30) - CP_LPAC_CHICKEN_DBG - SP_CHICKEN_BITS_2 - SP_LPAC_CHICKEN_BITS_2 A likely fix is to include those LPAC registers in the A750 IFPC restore list and the applicable general power-up list, so their initialized values survive collapse. The KGSL code in this checkout has a similar pattern: it conditionally adds LPAC chicken-bit registers to the Gen7 IFPC list when LPAC is enabled (adreno_gen7.c:652–660). Konrad