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[2001:14bb:a2:9556:dcef:1cfc:fd87:3323]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54d6e5247c9sm1215361e87.5.2025.04.22.07.16.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Apr 2025 07:16:07 -0700 (PDT) Message-ID: <14df4b1c-0a43-45e6-83c5-4c450615d901@oss.qualcomm.com> Date: Tue, 22 Apr 2025 17:16:05 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 22/23] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188 To: AngeloGioacchino Del Regno Cc: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, ck.hu@mediatek.com, jitao.shi@mediatek.com, jie.qiu@mediatek.com, junzhi.zhao@mediatek.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, dmitry.baryshkov@linaro.org, lewis.liao@mediatek.com, ives.chenjh@mediatek.com, tommyyl.chen@mediatek.com, jason-jh.lin@mediatek.com References: <20250415104321.51149-1-angelogioacchino.delregno@collabora.com> <20250415104321.51149-23-angelogioacchino.delregno@collabora.com> <7b3713d1-df18-4da1-a1e2-16dcff08fe66@collabora.com> Content-Language: en-US From: Dmitry Baryshkov In-Reply-To: <7b3713d1-df18-4da1-a1e2-16dcff08fe66@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=cdrSrmDM c=1 sm=1 tr=0 ts=6807a4aa cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=mpaa-ttXAAAA:8 a=QX4gbG5DAAAA:8 a=iyFSFCpoZHukXat7EuUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-ORIG-GUID: ycVhsD-e2yJsgO0HXace_soJqr479ztt X-Proofpoint-GUID: ycVhsD-e2yJsgO0HXace_soJqr479ztt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_07,2025-04-22_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 phishscore=0 adultscore=0 mlxlogscore=968 malwarescore=0 clxscore=1015 spamscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504220108 On 22/04/2025 16:53, AngeloGioacchino Del Regno wrote: > Il 21/04/25 21:16, Dmitry Baryshkov ha scritto: >> On Tue, Apr 15, 2025 at 12:43:20PM +0200, AngeloGioacchino Del Regno >> wrote: >>> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs >>> found in MediaTek's MT8195, MT8188 SoC and their variants, and >>> including support for display modes up to 4k60 and for HDMI >>> Audio, as per the HDMI 2.0 spec. >>> >>> HDCP and CEC functionalities are also supported by this hardware, >>> but are not included in this commit and that also poses a slight >>> difference between the V2 and V1 controllers in how they handle >>> Hotplug Detection (HPD). >>> >>> While the v1 controller was using the CEC controller to check >>> HDMI cable connection and disconnection, in this driver the v2 >>> one does not. >>> >>> This is due to the fact that on parts with v2 designs, like the >>> MT8195 SoC, there is one CEC controller shared between the HDMI >>> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually >>> adding support to use the CEC HW to wake up the HDMI controllers >>> it is necessary to have support for one TX, one RX *and* for both >>> at the same time. >>> >>> Reviewed-by: CK Hu >>> Signed-off-by: AngeloGioacchino Del Regno >>> >>> --- >>>   drivers/gpu/drm/mediatek/Kconfig            |    7 + >>>   drivers/gpu/drm/mediatek/Makefile           |    2 + >>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    4 + >>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    9 + >>>   drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  385 +++++ >>>   drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++ >>>   drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1396 +++++++++++++++++++ >>>   7 files changed, 2066 insertions(+) >>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c >>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h >>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c >>> >>> + >>> +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi) >>> +{ >>> +    struct hdmi_codec_params *params = &hdmi->aud_param.codec_params; >>> +    struct hdmi_audio_infoframe frame; >>> +    u8 buffer[14]; >>> +    ssize_t ret; >>> + >>> +    memcpy(&frame, ¶ms->cea, sizeof(frame)); >>> + >>> +    ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); >>> +    if (ret < 0) >>> +        return ret; >> >> This should really be done via >> drm_atomic_helper_connector_hdmi_update_audio_infoframe() or >> drm_atomic_helper_connector_hdmi_clear_audio_infoframe(). >> >> Ideally this should come from the .hw_params() / .prepare() calls so >> that you don't need to store the params in the driver data. >> > > When switching to the new hdmi audio helpers yes, but I was planning to > do that > later..... > >>> + >>> +    mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer); >>> + >>> +    return 0; >>> +} >>> + >>> +static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, >>> bool mute) >>> +{ >>> +    u32 val; >>> + >>> +    regmap_read(hdmi->regs, TOP_CFG01, &val); >>> +    val &= ~(CP_CLR_MUTE_EN | CP_SET_MUTE_EN); >>> + >>> +    if (mute) { >>> +        val |= CP_SET_MUTE_EN; >>> +        val &= ~CP_CLR_MUTE_EN; >>> +    } else { >>> +        val |= CP_CLR_MUTE_EN; >>> +        val &= ~CP_SET_MUTE_EN; >>> +    } >>> +    regmap_write(hdmi->regs, TOP_CFG01, val); >>> + >>> +    regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN); >>> +    regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR); >>> +} >>> + >>> +static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool >>> enable) >>> +{ >>> +    if (enable) >>> +        regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); >>> +    else >>> +        regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); >>> +} >>> + >>> +static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi >>> *hdmi) >>> +{ >>> +    u8 *ch_status = hdmi->aud_param.codec_params.iec.status; >>> + >>> +    /* Only the first 5 to 7 bytes of Channel Status contain useful >>> information */ >>> +    regmap_write(hdmi->regs, AIP_I2S_CHST0, >>> mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4)); >>> +    regmap_write(hdmi->regs, AIP_I2S_CHST1, >>> mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3)); >>> +} >>> + >>> +static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi, >>> +                     unsigned int sample_rate, >>> +                     unsigned int clock) >>> +{ >>> +    unsigned int n, cts; >>> + >>> +    mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts); >> >> drm_hdmi_acr_get_n_cts() ? >> > > I'd have to update both HDMI drivers to use that instead, and I was > planning to do > that at a later time when switching to the HDMI audio helpers. > >>> + >>> +    regmap_write(hdmi->regs, AIP_N_VAL, n); >>> +    regmap_write(hdmi->regs, AIP_CTS_SVAL, cts); >>> +} >>> + >> >> [...] >> >>> + >>> +static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data, >>> +                       struct hdmi_codec_daifmt *daifmt, >>> +                       struct hdmi_codec_params *params) >>> +{ >>> +    struct mtk_hdmi *hdmi = dev_get_drvdata(dev); >>> + >>> +    if (hdmi->audio_enable) { >>> +        mtk_hdmi_audio_params(hdmi, daifmt, params); >>> +        mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode); >>> +    } >>> +    return 0; >>> +} >>> + >>> +static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data) >>> +{ >>> +    struct mtk_hdmi *hdmi = dev_get_drvdata(dev); >>> + >>> +    mtk_hdmi_v2_hw_aud_enable(hdmi, true); >>> +    hdmi->audio_enable = true; >>> + >>> +    return 0; >>> +} >>> + >>> +static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data) >>> +{ >>> +    struct mtk_hdmi *hdmi = dev_get_drvdata(dev); >>> + >>> +    hdmi->audio_enable = false; >>> +    mtk_hdmi_v2_hw_aud_enable(hdmi, false); >> >> Most likely you need to stop sending the AUDIO packet too. Or is it dome >> by the hardware? >> > > The call to `mtk_hdmi_v2_hw_aud_enable(hdmi, false)` will set HW > registers to both > mute and stop sending the audio packet. > >>> +} >>> + >>> +static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, >>> bool enable, int dir) >>> +{ >>> +    struct mtk_hdmi *hdmi = dev_get_drvdata(dev); >>> + >>> +    mtk_hdmi_v2_hw_aud_mute(hdmi, enable); >>> + >>> +    return 0; >>> +} >>> + >>> +static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops = { >>> +    .hw_params = mtk_hdmi_v2_audio_hw_params, >>> +    .audio_startup = mtk_hdmi_v2_audio_startup, >>> +    .audio_shutdown = mtk_hdmi_v2_audio_shutdown, >>> +    .mute_stream = mtk_hdmi_v2_audio_mute, >>> +    .get_eld = mtk_hdmi_audio_get_eld, >>> +    .hook_plugged_cb = mtk_hdmi_v2_audio_hook_plugged_cb, >>> +}; >> >> Do you plan to switch to the OP_HDMI_AUDIO? I'd really like to see >> bridges use the framework instead of implementing everthing on their >> own. >> > > I do, but since I've already reached v9, I really don't want to do that > right now > and delay this driver for another two months. > > I plan to do the switch after we at least get this in: as the V1 driver > would also > need the same cleanup, I may even find a way to throw more stuff in the > hdmi_common > when cleaning up both at the same time. Ack. -- With best wishes Dmitry