From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751615AbdGYKS5 (ORCPT ); Tue, 25 Jul 2017 06:18:57 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13479 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750848AbdGYKS4 (ORCPT ); Tue, 25 Jul 2017 06:18:56 -0400 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 25 Jul 2017 03:18:55 -0700 From: Peter De Schrijver To: Peter De Schrijver , Michael Turquette , Stephen Boyd , , CC: Alex Frid Subject: [PATCH] clk: Don't write error code into divider register Date: Tue, 25 Jul 2017 13:18:40 +0300 Message-ID: <1500977920-5533-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alex Frid Add a check for error returned by divider value calculation to avoid writing error code into hw register. Signed-off-by: Alex Frid Reviewed-by: Peter De Schrijver Reviewed-by: Jon Mayo --- drivers/clk/clk-divider.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 9bb472c..4ed516c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -385,12 +385,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_divider *divider = to_clk_divider(hw); - unsigned int value; + int value; unsigned long flags = 0; u32 val; value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); + if (value < 0) + return value; if (divider->lock) spin_lock_irqsave(divider->lock, flags); @@ -403,7 +405,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, val = clk_readl(divider->reg); val &= ~(div_mask(divider->width) << divider->shift); } - val |= value << divider->shift; + val |= (u32)value << divider->shift; clk_writel(val, divider->reg); if (divider->lock) -- 1.9.1