From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752125AbdHDDer (ORCPT ); Thu, 3 Aug 2017 23:34:47 -0400 Received: from regular1.263xmail.com ([211.150.99.132]:49882 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752086AbdHDDeo (ORCPT ); Thu, 3 Aug 2017 23:34:44 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: finley.xiao@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: finley.xiao@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Finley Xiao To: heiko@sntech.de, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, jay.xu@rock-chips.com, huangtao@rock-chips.com, tony.xie@rock-chips.com, cl@rock-chips.com, Finley Xiao Subject: [PATCH 1/2] arm64: dts: rockchip: Add cpu operating points for RK3328 SoC Date: Fri, 4 Aug 2017 11:33:37 +0800 Message-Id: <1501817618-65504-2-git-send-email-finley.xiao@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501817618-65504-1-git-send-email-finley.xiao@rock-chips.com> References: <1501817618-65504-1-git-send-email-finley.xiao@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds basic OPP entries for RK3328 SoC. Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 440e6bc..81fd8cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -76,6 +76,7 @@ clocks = <&cru ARMCLK>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -85,6 +86,7 @@ clocks = <&cru ARMCLK>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@2 { @@ -94,6 +96,7 @@ clocks = <&cru ARMCLK>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@3 { @@ -103,6 +106,7 @@ clocks = <&cru ARMCLK>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; }; l2: l2-cache0 { @@ -110,6 +114,43 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; + }; + amba { compatible = "simple-bus"; #address-cells = <2>; -- 2.7.4