From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752220AbdHHHNh (ORCPT ); Tue, 8 Aug 2017 03:13:37 -0400 Received: from regular1.263xmail.com ([211.150.99.133]:52532 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751918AbdHHHNg (ORCPT ); Tue, 8 Aug 2017 03:13:36 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zhangqing@rock-chips.com X-FST-TO: mturquette@baylibre.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhangqing@rock-chips.com X-UNIQUE-TAG: <9451d36f6645a6ed53c1293c5f221426> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Elaine Zhang To: mturquette@baylibre.com, sboyd@codeaurora.org, heiko@sntech.de Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, shawn.lin@rock-chips.com, andy.yan@rock-chips.com, Elaine Zhang Subject: [PATCH v3 5/9] clk: rockchip: fix up the pll clks error for rv1108 SoC Date: Tue, 8 Aug 2017 15:17:55 +0800 Message-Id: <1502176675-32228-1-git-send-email-zhangqing@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502176547-30817-1-git-send-email-zhangqing@rock-chips.com> References: <1502176547-30817-1-git-send-email-zhangqing@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org fix up the lock_shift describe error. remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rv1108.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c index 3c670db16e18..9c6bad0da140 100644 --- a/drivers/clk/rockchip/clk-rv1108.c +++ b/drivers/clk/rockchip/clk-rv1108.c @@ -148,11 +148,11 @@ enum rv1108_plls { static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), - RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates), + RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates), [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), - RV1108_PLL_CON(11), 8, 31, 0, NULL), + RV1108_PLL_CON(11), 8, 1, 0, NULL), [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), - RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates), + RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates), }; #define MFLAGS CLK_MUX_HIWORD_MASK -- 1.9.1