From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754041AbdHRDos (ORCPT ); Thu, 17 Aug 2017 23:44:48 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:37220 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753828AbdHRDon (ORCPT ); Thu, 17 Aug 2017 23:44:43 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zhangqing@rock-chips.com X-FST-TO: mturquette@baylibre.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhangqing@rock-chips.com X-UNIQUE-TAG: <13a09dcba1e6a69da7b15fbea69def99> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Elaine Zhang To: mturquette@baylibre.com, sboyd@codeaurora.org, heiko@sntech.de Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, frank.wang@rock-chips.com, cl@rock-chips.com, Elaine Zhang Subject: [PATCH v1 1/2] clk: rockchip: add rk3228 sclk_sdio_src ID Date: Fri, 18 Aug 2017 11:49:24 +0800 Message-Id: <1503028165-27072-2-git-send-email-zhangqing@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1503028165-27072-1-git-send-email-zhangqing@rock-chips.com> References: <1503028165-27072-1-git-send-email-zhangqing@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch exports sdio src clock for dts reference. Signed-off-by: Elaine Zhang --- include/dt-bindings/clock/rk3228-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 56f841c22801..55655ab0a4c4 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -49,6 +49,7 @@ #define SCLK_EMMC_DRV 117 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 -- 1.9.1