From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751266AbdILCkS (ORCPT ); Mon, 11 Sep 2017 22:40:18 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:64897 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750969AbdILCkR (ORCPT ); Mon, 11 Sep 2017 22:40:17 -0400 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v8C2buJY001020 X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH 2/2] mtd: nand: denali: support two row address cycle devices Date: Tue, 12 Sep 2017 11:37:31 +0900 Message-Id: <1505183851-29355-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505183851-29355-1-git-send-email-yamada.masahiro@socionext.com> References: <1505183851-29355-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The register TWO_ROW_ADDR_CYCLES specifies the number of row address cycles of the device, but it is fixed to 0 in the driver init code (i.e. always 3 row address cycles). Reflect the result of nand_scan_ident() to the register setting in order to support 2 row address cycle devices. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3087b0b..aefdc83 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1137,8 +1137,6 @@ static void denali_hw_init(struct denali_nand_info *denali) iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); - /* Should set value for these registers when init */ - iowrite32(0, denali->reg + TWO_ROW_ADDR_CYCLES); iowrite32(1, denali->reg + ECC_ENABLE); } @@ -1379,6 +1377,8 @@ int denali_init(struct denali_nand_info *denali) denali->reg + PAGES_PER_BLOCK); iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, denali->reg + DEVICE_WIDTH); + iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, + denali->reg + TWO_ROW_ADDR_CYCLES); iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); -- 2.7.4