From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751819AbdIVBO1 (ORCPT ); Thu, 21 Sep 2017 21:14:27 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:37522 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751779AbdIVBOZ (ORCPT ); Thu, 21 Sep 2017 21:14:25 -0400 X-UUID: 6d780f6d297e44999a16fd9cb7efc88b-20170922 Message-ID: <1506042853.17567.23.camel@mhfsdcap03> Subject: Re: [PATCH RESEND 1/2] phy: phy-mtk-tphy: fix NULL point of chip bank From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Matthias Brugger , Ryder Lee , , , , Date: Fri, 22 Sep 2017 09:14:13 +0800 In-Reply-To: <02a5e183-444a-bc75-2a4e-1337c9e7872e@ti.com> References: <5ddda7cc6940941b645564afff5afa496d7dbb68.1505989703.git.chunfeng.yun@mediatek.com> <02a5e183-444a-bc75-2a4e-1337c9e7872e@ti.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2017-09-21 at 16:23 +0530, Kishon Vijay Abraham I wrote: > > On Thursday 21 September 2017 04:01 PM, Chunfeng Yun wrote: > > Chip bank of version-1 is initialized as NULL, but it's used > > by pcie_phy_instance_power_on/off(), so assign it a right > > address. > > merged. How was this not noticed before? The PCIe function was tested on mt2712 with tphy-v2, and didn't notice this issue until tested it on mt7622 with tphy-v1. Ashamed of myself for making such a rookie mistake. > > Thanks > Kishon > > > > Signed-off-by: Chunfeng Yun > > --- > > drivers/phy/mediatek/phy-mtk-tphy.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c > > index e3baad7..721a2a1 100644 > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > > @@ -27,6 +27,7 @@ > > /* banks shared by multiple phys */ > > #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ > > #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ > > +#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ > > /* u2 phy bank */ > > #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 > > /* u3/pcie/sata phy banks */ > > @@ -762,7 +763,7 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy, > > case PHY_TYPE_USB3: > > case PHY_TYPE_PCIE: > > u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; > > - u3_banks->chip = NULL; > > + u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; > > u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; > > u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; > > break; > >