From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752056AbdJDVWZ (ORCPT ); Wed, 4 Oct 2017 17:22:25 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:38940 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752120AbdJDVVg (ORCPT ); Wed, 4 Oct 2017 17:21:36 -0400 From: "Paul E. McKenney" To: linux-kernel@vger.kernel.org Cc: mingo@kernel.org, jiangshanlai@gmail.com, dipankar@in.ibm.com, akpm@linux-foundation.org, mathieu.desnoyers@efficios.com, josh@joshtriplett.org, tglx@linutronix.de, peterz@infradead.org, rostedt@goodmis.org, dhowells@redhat.com, edumazet@google.com, fweisbec@gmail.com, oleg@redhat.com, "Guilherme G. Piccoli" , "Paul E. McKenney" Subject: [PATCH tip/core/rcu 16/16] Documentation: rewrite confusing statement about memory barriers Date: Wed, 4 Oct 2017 14:21:26 -0700 X-Mailer: git-send-email 2.5.2 In-Reply-To: <20171004212051.GA8411@linux.vnet.ibm.com> References: <20171004212051.GA8411@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17100421-0040-0000-0000-000003ACCFDA X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007843; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000233; SDB=6.00926530; UDB=6.00466099; IPR=6.00706743; BA=6.00005620; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017394; XFM=3.00000015; UTC=2017-10-04 21:21:32 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17100421-0041-0000-0000-000007A1E053 Message-Id: <1507152086-9791-16-git-send-email-paulmck@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-10-04_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710040296 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "Guilherme G. Piccoli" In this specific portion of the write memory barriers description, the documentation mentions sequential order of stores, which is confusing since sequential ordering is not guaranteed. This patch tries to improve the doc in order to avoid any mis-understanding. Cc: Paul E. McKenney Signed-off-by: Guilherme G. Piccoli Signed-off-by: Paul E. McKenney --- Documentation/memory-barriers.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index f37375544d71..519940ec767f 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -383,8 +383,8 @@ Memory barriers come in four basic varieties: to have any effect on loads. A CPU can be viewed as committing a sequence of store operations to the - memory system as time progresses. All stores before a write barrier will - occur in the sequence _before_ all the stores after the write barrier. + memory system as time progresses. All stores _before_ a write barrier + will occur _before_ all the stores after the write barrier. [!] Note that write barriers should normally be paired with read or data dependency barriers; see the "SMP barrier pairing" subsection. -- 2.5.2