From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752248AbdJEKyJ (ORCPT ); Thu, 5 Oct 2017 06:54:09 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:37679 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751797AbdJEKyF (ORCPT ); Thu, 5 Oct 2017 06:54:05 -0400 X-Google-Smtp-Source: AOwi7QB3YUMzKAiCWF9PK7Uy21Bfcnzzh2r76TU+NgOSyy5PBeYBabBNCT3tPc3/2vEpHf9HmuJoEA== From: Wanpeng Li X-Google-Original-From: Wanpeng Li To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Wanpeng Li Subject: [PATCH v3 0/3] KVM: LAPIC: Rework lapic timer to behave more like real-hardware Date: Thu, 5 Oct 2017 03:53:50 -0700 Message-Id: <1507200833-20434-1-git-send-email-wanpeng.li@hotmail.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The issue is reported in xen community. Anthony PERARD pointed out: https://www.mail-archive.com/xen-devel@lists.xen.org/msg117283.html# | When developing PVH for OVMF, I've used the lapic timer. It turns out that the | way it is used by OVMF did not work with Xen [1]. I tried to find out how | real-hw behave, and write a XTF tests [2]. And this patch series tries to fix | the behavior of the vlapic timer. | | | The OVMF driver for the APIC timer initialize the timer like this: | write to TMICT (initial counter) | write to TMDCR (divide configuration) | enable the timer (this may change timer mode from one-shot to periodic) | It turns out that TMICT is set to 0 on the last step, but OVMF expect the timer | to run. | | Here is some description of the APIC timer, base on observation as well as read | of the Intel SDM. The description is also patch of patch description | (reworded). | | Maybe a way of thinking how the APIC timer is evaluated, is to think of how | hardward will do it. There is a counter TMCCT which always keeps counting down. | | Setting TMICT also set TMCCT, nothing else matter. | Setting LVTT does not change anything right away. | Setting TMDCR does not change much. | | Now TMCCT keeps counting down, by a value related to TMDCR. | Once, TMCCT reach 0, it is only at this time that LVTT is taken into account. | Is there an interrupt to deliver? Should the timer restart counting from the | value in TMICT? | | In the Intel SDM, there is the word "disarm" of the timer used. I guess the | easier way to disarm the APIC timer (when in periodic or one-shot) is to set | TMICT to 0. But if we take TSC-Deadline mode out of the picture, there is | nothing in the manual that say that the timer is disarm or stopped when | changing timer mode (there is only two modes left, period and one-shot). | | As for the TSC-deadline timer mode, observation shown that changing to it (or | from it) does reset and disarm both timers, so effectively TMICT and the | tscdeadline are set to 0. | | [1] https://lists.xenproject.org/archives/html/xen-devel/2016-12/msg00959.html | [2] v1: | https://lists.xenproject.org/archives/html/xen-devel/2017-03/msg02533.html | v2: look for "[XTF PATCH V2 0/3] Testing vlapic timer" v2 -> v3: * move the write 0 to APIC_TMICT logic to apic_update_lvtt() * skip hrtimer_cancel() in apic_update_lvtt() when either from one-shot mode to periodic or vice versa. v1 -> v2: * add cover-letter and collect recent lapic patches to one patchset Wanpeng Li (3): KVM: LAPIC: Fix lapic timer mode transition KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode KVM: LAPIC: Apply change to TDCR right away to the timer arch/x86/include/asm/apicdef.h | 1 + arch/x86/kvm/lapic.c | 63 +++++++++++++++++++++++++++++++----------- 2 files changed, 48 insertions(+), 16 deletions(-) -- 2.7.4