From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752149AbdJ0IGq (ORCPT ); Fri, 27 Oct 2017 04:06:46 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:45749 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750930AbdJ0IGo (ORCPT ); Fri, 27 Oct 2017 04:06:44 -0400 Message-ID: <1509091595.7559.2.camel@pengutronix.de> Subject: Re: [PATCH] drm/bridge/synopsys: dsi: add optional pixel clock From: Philipp Zabel To: Philippe Cornu , Archit Taneja , Andrzej Hajda , Laurent Pinchart , David Airlie , Benjamin Gaignard , Bhumika Goyal , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Yannick Fertre , Vincent Abriou , Alexandre Torgue , Maxime Coquelin , Gabriel Fernandez , Ludovic Barre , Fabien Dessenne , Mickael Reulier Date: Fri, 27 Oct 2017 10:06:35 +0200 In-Reply-To: <1509034175-23767-1-git-send-email-philippe.cornu@st.com> References: <1509034175-23767-1-git-send-email-philippe.cornu@st.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1+deb9u1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Philippe, On Thu, 2017-10-26 at 18:09 +0200, Philippe Cornu wrote: > The pixel clock is optional. When available, it offers a better > preciseness for timing computations. > > Signed-off-by: Philippe Cornu > --- > drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 24 ++++++++++++++++++------ > 1 file changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > index d9cca4f..8b3787d 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > @@ -225,6 +225,7 @@ struct dw_mipi_dsi { > void __iomem *base; > > struct clk *pclk; > + struct clk *px_clk; > > unsigned int lane_mbps; /* per lane */ > u32 channel; > @@ -753,24 +754,28 @@ void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, > struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); > const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; > void *priv_data = dsi->plat_data->priv_data; > + struct drm_display_mode px_clk_mode = *mode; > int ret; > > clk_prepare_enable(dsi->pclk); > > - ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags, > + if (dsi->px_clk) > + px_clk_mode.clock = clk_get_rate(dsi->px_clk) / 1000; I don't understand why is the pixel clock rate divided by 1000 different from the mode clock in the first place? If px_clk is just the DPI input pixel clock signal from the display controller, I'd expect the mode to be adjusted correctly. > + > + ret = phy_ops->get_lane_mbps(priv_data, &px_clk_mode, dsi->mode_flags, > dsi->lanes, dsi->format, &dsi->lane_mbps); > if (ret) > DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); > > pm_runtime_get_sync(dsi->dev); > dw_mipi_dsi_init(dsi); > - dw_mipi_dsi_dpi_config(dsi, mode); > + dw_mipi_dsi_dpi_config(dsi, &px_clk_mode); > dw_mipi_dsi_packet_handler_config(dsi); > dw_mipi_dsi_video_mode_config(dsi); > - dw_mipi_dsi_video_packet_config(dsi, mode); > + dw_mipi_dsi_video_packet_config(dsi, &px_clk_mode); > dw_mipi_dsi_command_mode_config(dsi); > - dw_mipi_dsi_line_timer_config(dsi, mode); > - dw_mipi_dsi_vertical_timing_config(dsi, mode); > + dw_mipi_dsi_line_timer_config(dsi, &px_clk_mode); > + dw_mipi_dsi_vertical_timing_config(dsi, &px_clk_mode); > > dw_mipi_dsi_dphy_init(dsi); > dw_mipi_dsi_dphy_timing_config(dsi); > @@ -784,7 +789,7 @@ void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, > > dw_mipi_dsi_dphy_enable(dsi); > > - dw_mipi_dsi_wait_for_two_frames(mode); > + dw_mipi_dsi_wait_for_two_frames(&px_clk_mode); > > /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ > dw_mipi_dsi_set_mode(dsi, 0); > @@ -878,6 +883,13 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) > return ERR_PTR(ret); > } > > + dsi->px_clk = devm_clk_get(dev, "px_clk"); Is "px_clk" what the pixel clock is called in the datasheet? If this is probed from DT, the new optional property must be documented in the binding docs. > + if (IS_ERR(dsi->px_clk)) { > + ret = PTR_ERR(dsi->px_clk); Better leave ret == 0 for -ENOENT, but return the error for all others. > + dev_dbg(dev, "Unable to get optional px_clk: %d\n", ret); > + dsi->px_clk = NULL; > + } > + > /* > * Note that the reset was not defined in the initial device tree, so > * we have to be prepared for it not being found. regards Philipp