From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: pbonzini@redhat.com, rkrcmar@redhat.com, tglx@linutronix.de,
mingo@redhat.com, hpa@zytor.com, x86@kernel.org,
linux-kernel@vger.kernel.org,
Chao Peng <chao.p.peng@linux.intel.com>,
Luwei Kang <luwei.kang@intel.com>
Subject: [patch v2 7/8] KVM: x86: add Intel PT msr RTIT_CTL read/write
Date: Tue, 31 Oct 2017 06:05:16 +0800 [thread overview]
Message-ID: <1509401117-15521-8-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1509401117-15521-1-git-send-email-luwei.kang@intel.com>
From: Chao Peng <chao.p.peng@linux.intel.com>
L1 hypervisor can't get the capability of "TraceEn can be
set in VMX operation"(IA32_VMX_MISC[14]=0) and any attempt
to set IA32_RTIT_CTL.TraceEn in VMX operation using WRMSR
will cause a general-protection exception if IA32_VMX_MISC[14]
is 0. So we need to leave out write this msr in L1 VMX
operation.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/kvm/vmx.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 091120e..8f61a8d 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -936,6 +936,7 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
u16 error_code);
+static bool vmx_pt_supported(void);
static DEFINE_PER_CPU(struct vmcs *, vmxarea);
static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -3384,6 +3385,11 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return 1;
msr_info->data = vcpu->arch.ia32_xss;
break;
+ case MSR_IA32_RTIT_CTL:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data = vmcs_read64(GUEST_IA32_RTIT_CTL);
+ break;
case MSR_TSC_AUX:
if (!msr_info->host_initiated &&
!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
@@ -3508,6 +3514,11 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
else
clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
break;
+ case MSR_IA32_RTIT_CTL:
+ if (!vmx_pt_supported() || to_vmx(vcpu)->nested.vmxon)
+ return 1;
+ vmcs_write64(GUEST_IA32_RTIT_CTL, data);
+ break;
case MSR_TSC_AUX:
if (!msr_info->host_initiated &&
!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
--
1.8.3.1
next prev parent reply other threads:[~2017-10-31 11:49 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-30 22:05 [patch v2 0/8] Intel Processor Trace virtulization enabling Luwei Kang
2017-10-30 22:05 ` [patch v2 1/8] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2017-10-30 22:05 ` [patch v2 2/8] perf/x86/intel/pt: change pt_cap_get() to a public function Luwei Kang
2017-10-30 22:05 ` [patch v2 3/8] KVM: x86: add Intel processor trace virtualization mode Luwei Kang
2017-11-13 16:29 ` Paolo Bonzini
2017-11-14 7:11 ` Kang, Luwei
2017-11-13 16:32 ` Paolo Bonzini
2017-11-14 7:31 ` Kang, Luwei
2017-11-14 10:47 ` Paolo Bonzini
2017-10-30 22:05 ` [patch v2 4/8] KVM: x86: add Intel processor trace cpuid emulataion Luwei Kang
2017-11-13 15:36 ` Paolo Bonzini
2017-11-14 2:56 ` Kang, Luwei
2017-10-30 22:05 ` [patch v2 5/8] KVM: x86: add Intel processor trace context for each vcpu Luwei Kang
2017-10-30 22:05 ` [patch v2 6/8] KVM: x86: Implement Intel processor trace context switch Luwei Kang
2017-11-13 16:01 ` Paolo Bonzini
2017-10-30 22:05 ` Luwei Kang [this message]
2017-11-13 16:22 ` [patch v2 7/8] KVM: x86: add Intel PT msr RTIT_CTL read/write Paolo Bonzini
2017-11-14 6:59 ` Kang, Luwei
2017-11-14 10:34 ` Paolo Bonzini
2017-10-30 22:05 ` [patch v2 8/8] KVM: x86: Disable intercept for Intel processor trace MSRs Luwei Kang
2017-11-13 16:24 ` Paolo Bonzini
2017-11-14 7:01 ` Kang, Luwei
2017-11-02 14:57 ` [patch v2 0/8] Intel Processor Trace virtulization enabling Paolo Bonzini
2017-11-03 6:09 ` Kang, Luwei
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