From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752887AbdJaHUB (ORCPT ); Tue, 31 Oct 2017 03:20:01 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54908 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751564AbdJaHT6 (ORCPT ); Tue, 31 Oct 2017 03:19:58 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 25E14606AC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=anischal@codeaurora.org From: Amit Nischal To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Amit Nischal Subject: [PATCH 0/2] clk: qcom: MISC RCG changes for upcoming targets Date: Tue, 31 Oct 2017 12:49:38 +0530 Message-Id: <1509434380-24372-1-git-send-email-anischal@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch series modifies clk_rcg2_shared_ops to support clock controller drivers used in future chipsets and also clear hardware clock control bit of RCGs where HW clock control bit is set in order to control those root clocks by software. Amit Nischal (2): clk: qcom: clear hardware clock control bit of RCG clk: qcom: Modify RCG shared ops to support freq_tbl without XO entry drivers/clk/qcom/clk-rcg2.c | 84 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 73 insertions(+), 11 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation