From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934093AbdKBSQ4 (ORCPT ); Thu, 2 Nov 2017 14:16:56 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:53666 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933623AbdKBSQF (ORCPT ); Thu, 2 Nov 2017 14:16:05 -0400 X-Google-Smtp-Source: ABhQp+ReaNiy8M/ojQShc83fYHAJJm7EtYXFPfjy7TIK0gFylNJeViAQnt9F8iakqgA8Ka8Z1P1FNA== From: Stephane Eranian To: linux-kernel@vger.kernel.org Cc: acme@redhat.com, peterz@infradead.org, mingo@elte.hu, ak@linux.intel.com, kan.liang@intel.com, jolsa@redhat.com, Stephane Eranian Subject: [PATCH v2 2/5] perf/x86: add PERF_SAMPLE_SKID_IP support for X86 PEBS Date: Thu, 2 Nov 2017 11:15:56 -0700 Message-Id: <1509646559-919-3-git-send-email-eranian@google.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509646559-919-1-git-send-email-eranian@google.com> References: <1509646559-919-1-git-send-email-eranian@google.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stephane Eranian This atch adds support for SKID_IP to Intel x86 processors in PEBS mode. Signed-off-by: Stephane Eranian --- arch/x86/events/intel/ds.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index e1965e5ff570..b7afdf88f441 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1189,6 +1189,13 @@ static void setup_pebs_sample_data(struct perf_event *event, x86_pmu.intel_cap.pebs_format >= 1) data->addr = pebs->dla; + /* + * unmodified, skid IP which is guaranteed to be the next + * dyanmic instruction + */ + if (sample_type & PERF_SAMPLE_SKID_IP) + data->skid_ip = pebs->ip; + if (x86_pmu.intel_cap.pebs_format >= 2) { /* Only set the TSX weight when no memory weight. */ if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) -- 2.7.4