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From: Jinjie Ruan <ruanjinjie@huawei.com>
To: <cp0613@linux.alibaba.com>
Cc: <akpm@linux-foundation.org>, <alex@ghiti.fr>,
	<aou@eecs.berkeley.edu>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <palmer@dabbelt.com>,
	<pjw@kernel.org>
Subject: Re: [PATCH] arch/riscv: Add bitrev.h file to support rev8 and brev8
Date: Sat, 11 Apr 2026 10:48:17 +0800	[thread overview]
Message-ID: <150bfb90-ec49-7209-b841-2e48ca12b370@huawei.com> (raw)
In-Reply-To: <20260410113640.106730-1-cp0613@linux.alibaba.com>



On 2026/4/10 19:36, cp0613@linux.alibaba.com wrote:
> On Wed, 11 Mar 2026 15:13:44 +0800, ruanjinjie@huawei.com wrote:
> 
>> +#include <linux/types.h>
>> +#include <asm/cpufeature-macros.h>
>> +#include <asm/hwcap.h>
>> +
>> +extern u8 const byte_rev_table[256];
>> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x)
>> +{
>> +	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBKB) &&
>> +	    riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB)) {
>> +		unsigned long result = x;
>> +
>> +		asm volatile(
>> +			".option push\n"
>> +			".option arch,+zbkb\n"
>> +			"rev8 %0, %0\n"
>> +			"brev8 %0, %0\n"
>> +			".option pop"
>> +			: "+r" (result)
>> +		);
>> +
>> +		if (__riscv_xlen == 64)
>> +			return (u32)(result >> 32);
>> +
>> +		return (u32)result;
>> +	}
>> +
>> +	return (u32)byte_rev_table[x & 0xff] << 24 |
>> +	       (u32)byte_rev_table[(x >> 8) & 0xff] << 16 |
>> +	       (u32)byte_rev_table[(x >> 16) & 0xff] << 8 |
>> +	       (u32)byte_rev_table[x >> 24];
>> +}
> 
> Hi Jinjie,
> 
> Thanks for your patch. I have two suggestions.
> 1. When ZBKB is not supported, is it simpler to directly use the generic
> implementation __bitrev32 in <linux/bitrev.h>.

Actually, you can't simply use the default implementation from
linux/bitrev.h. It includes asm/bitrev.h (the architecture-specific
implementation), which would lead to compilation issues. Furthermore,
when ZBKB is not supported, current implementation is identical to the
default one.


> 2. Could you please provide a benchmark test case to illustrate the
> performance comparison with and without this extension (refer to
> test_bitops.c) and also provide the results by bloat-o-meter.

I don't have access to RISC-V hardware at the moment, so I've only
performed basic functional testing on QEMU, which completed without
issues,could you please help run some benchmarks to verify the performance?

Thanks,
Jinjie

> 
> Thanks,
> Pei

  reply	other threads:[~2026-04-11  2:48 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-11  7:13 Jinjie Ruan
2026-04-02  6:41 ` Jinjie Ruan
2026-04-10 11:36 ` cp0613
2026-04-11  2:48   ` Jinjie Ruan [this message]
2026-04-13 12:28     ` cp0613
2026-04-15  7:39       ` Jinjie Ruan

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