From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754253AbdKJXUx (ORCPT ); Fri, 10 Nov 2017 18:20:53 -0500 Received: from mga01.intel.com ([192.55.52.88]:48834 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751186AbdKJXUv (ORCPT ); Fri, 10 Nov 2017 18:20:51 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,376,1505804400"; d="scan'208";a="1037717" Message-ID: <1510356963.2515.5.camel@megha-Z97X-UD7-TH> Subject: Re: [PATCH V0 2/3] perf/x86/intel/bm.c: Add Intel Branch Monitoring support From: Megha Dey To: Alexander Shishkin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, andriy.shevchenko@linux.intel.com, kstewart@linuxfoundation.org, yu-cheng.yu@intel.com, len.brown@intel.com, gregkh@linuxfoundation.org, peterz@infradead.org, acme@kernel.org, jolsa@redhat.com, namhyung@kernel.org, vikas.shivappa@linux.intel.com, pombredanne@nexb.com, me@kylehuey.com, bp@suse.de, grzegorz.andrejczuk@intel.com, tony.luck@intel.com, corbet@lwn.net, ravi.v.shankar@intel.com Date: Fri, 10 Nov 2017 15:36:03 -0800 In-Reply-To: <20171106114943.mg6pwpqe6eqlx7w2@ukko.fi.intel.com> References: <1509732006-5917-1-git-send-email-megha.dey@linux.intel.com> <1509732006-5917-3-git-send-email-megha.dey@linux.intel.com> <20171106114943.mg6pwpqe6eqlx7w2@ukko.fi.intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-11-06 at 13:49 +0200, Alexander Shishkin wrote: > On Fri, Nov 03, 2017 at 11:00:05AM -0700, Megha Dey wrote: > > +static int intel_bm_event_init(struct perf_event *event) > > +{ > > ... > > > + /* > > + * Find a hardware counter for the target task > > + */ > > + for (i = 0; i < bm_num_counters; i++) { > > + if ((bm_counter_owner[i] == NULL) || > > + (bm_counter_owner[i]->state == PERF_EVENT_STATE_DEAD)) { > > + counter_to_use = i; > > + bm_counter_owner[i] = event; > > + break; > > How are two concurrent perf_event_open()s not going to race here? > Also, I'm not sure what's the value of looking at the ->state here. > Shouldn't the ->destroy() method clear the corresponding array slot? Yes you are right. I will add a locking mechanism here to prevent racing and remove the ->state in the next version. > > > + } > > + } > > ... > > > + wrmsrl(BR_DETECT_COUNTER_CONFIG_BASE + counter_to_use, > > + event->hw.bm_counter_conf); > > + wrmsrl(BR_DETECT_STATUS_MSR, 0); > > These wrmsrs will happen on whatever CPU perf_event_open() is called on, > as opposed to the CPU where the event will be scheduled. You probably want > to keep the MSR accesses in the start()/stop() callbacks. Agreed, don't think we need this code here. We are writing to the MSRs in start() anyways. > > Regards, > -- > Alex >