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b=4nKdUgx+ZYDXIZHXxtrZMo00DaD7dB4+SSEm2pmGndvxJ5iecV3O2t6AaxhGPQWY9rxNIKFQOETVL80cFD/gbkeLD9wEDTBkNGGPO/d0DrVguiSBWs2oAbmnSKfnyFzpMPM/LNS01hAWqhyQsFrETdjt6rSsoLfUZK0Lxu57tFE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DM4PR12MB5070.namprd12.prod.outlook.com (2603:10b6:5:389::22) by CYYPR12MB8939.namprd12.prod.outlook.com (2603:10b6:930:b8::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.18; Tue, 10 Dec 2024 17:22:15 +0000 Received: from DM4PR12MB5070.namprd12.prod.outlook.com ([fe80::20a9:919e:fd6b:5a6e]) by DM4PR12MB5070.namprd12.prod.outlook.com ([fe80::20a9:919e:fd6b:5a6e%5]) with mapi id 15.20.8230.010; Tue, 10 Dec 2024 17:22:15 +0000 Message-ID: <1510fe7f-1c10-aea7-75be-37c5c58d6a05@amd.com> Date: Tue, 10 Dec 2024 11:22:13 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v15 06/13] x86/sev: Prevent GUEST_TSC_FREQ MSR interception for Secure TSC enabled guests Content-Language: en-US To: Nikunj A Dadhania , Borislav Petkov Cc: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org, mingo@redhat.com, tglx@linutronix.de, dave.hansen@linux.intel.com, pgonda@google.com, seanjc@google.com, pbonzini@redhat.com References: <20241203090045.942078-1-nikunj@amd.com> <20241203090045.942078-7-nikunj@amd.com> <20241210121127.GBZ1gv74Q6IRtAS1pl@fat_crate.local> From: Tom Lendacky In-Reply-To: Content-Type: text/plain; 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>>> >>> + /* >>> + * GUEST_TSC_FREQ should not be intercepted when Secure TSC is >>> + * enabled. Terminate the SNP guest when the interception is enabled. >>> + */ >>> + if (regs->cx == MSR_AMD64_GUEST_TSC_FREQ && (sev_status & MSR_AMD64_SNP_SECURE_TSC)) >>> + return ES_VMM_ERROR; >>> + >>> + >> >> If you merge this logic into the switch-case, the patch becomes even easier >> and the code cleaner: > > This is incorrect, for a non-Secure TSC guest, a read of intercepted > MSR_AMD64_GUEST_TSC_FREQ will return value of rdtsc_ordered(). This is an invalid > MSR when SecureTSC is not enabled. For the non-Secure TSC guest, I still think that we should continue to use the GHCB MSR NAE event instead of switching to using rdtsc_ordered(). Thanks, Tom > >> >> diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c >> index 050170eb28e6..35d9a3bb4b06 100644 >> --- a/arch/x86/coco/sev/core.c >> +++ b/arch/x86/coco/sev/core.c >> @@ -1446,6 +1446,13 @@ static enum es_result __vc_handle_msr_tsc(struct pt_regs *regs, bool write) >> if (!(sev_status & MSR_AMD64_SNP_SECURE_TSC)) >> goto read_tsc; >> >> + /* >> + * GUEST_TSC_FREQ should not be intercepted when Secure TSC is >> + * enabled. Terminate the SNP guest when the interception is enabled. >> + */ >> + if (regs->cx == MSR_AMD64_GUEST_TSC_FREQ) >> + return ES_VMM_ERROR; >> + >> if (write) { >> WARN_ONCE(1, "TSC MSR writes are verboten!\n"); >> return ES_UNSUPPORTED; >> @@ -1472,6 +1479,7 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) >> case MSR_SVSM_CAA: >> return __vc_handle_msr_caa(regs, write); >> case MSR_IA32_TSC: >> + case MSR_AMD64_GUEST_TSC_FREQ: >> return __vc_handle_msr_tsc(regs, write); >> default: >> break; >> > > Regards > Nikunj