From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751226AbdKTKdQ (ORCPT ); Mon, 20 Nov 2017 05:33:16 -0500 Received: from mail-wm0-f50.google.com ([74.125.82.50]:37854 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751070AbdKTKdN (ORCPT ); Mon, 20 Nov 2017 05:33:13 -0500 X-Google-Smtp-Source: AGs4zMa0Flcp4bfq5oSVPnWzObE4tpHcisD5ngqu5nDjfeinIGCoXeXfn3cnG4O8JM19+TEo4mw6nQ== Message-ID: <1511173991.6971.7.camel@baylibre.com> Subject: Re: [PATCH v2 1/2] pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC From: Jerome Brunet To: Yixun Lan , Linus Walleij , Kevin Hilman Cc: Neil Armstrong , Carlo Caione , Xingyu Chen , linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Mon, 20 Nov 2017 11:33:11 +0100 In-Reply-To: <20171120100825.16613-2-yixun.lan@amlogic.com> References: <20171120100825.16613-1-yixun.lan@amlogic.com> <20171120100825.16613-2-yixun.lan@amlogic.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.2 (3.26.2-1.fc27) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2017-11-20 at 18:08 +0800, Yixun Lan wrote: > From: Xingyu Chen > > The pin controller has been updated in the Amlogic Meson AXG series, > which use continuous 4-bit register to select function for each pin. > In order to support this, a new pinmux operations "meson_axg_pmx_ops" > has been added. > > Reviewed-by: Neil Armstrong Reviewed-by: Jerome Brunet > Signed-off-by: Xingyu Chen > Signed-off-by: Yixun Lan