From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752534AbdK0NhP (ORCPT ); Mon, 27 Nov 2017 08:37:15 -0500 Received: from mail-wm0-f52.google.com ([74.125.82.52]:37167 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752468AbdK0NhN (ORCPT ); Mon, 27 Nov 2017 08:37:13 -0500 X-Google-Smtp-Source: AGs4zMa27ypm0HpptEHsnWGtGCzJJAJa5ANUNVmiH3a87bh9/x3Ttl09KcIWQJ1vvPyEqJu5zDVSsQ== Message-ID: <1511789830.30519.3.camel@baylibre.com> Subject: Re: [PATCH v4 1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA From: Jerome Brunet To: Yixun Lan , Neil Armstrong Cc: Michael Turquette , Stephen Boyd , Martin Blumenstingl , Carlo Caione , Kevin Hilman , Xingyu Chen , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Mon, 27 Nov 2017 14:37:10 +0100 In-Reply-To: <20171107141223.1507-1-yixun.lan@amlogic.com> References: <20171107141223.1507-1-yixun.lan@amlogic.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.26.2 (3.26.2-1.fc27) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2017-11-07 at 22:12 +0800, Yixun Lan wrote: > According to the datasheet, in Meson-GXBB/GXL series, > The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], > while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. > > Test passed at gxl-s905x-p212 board. > > The following published datasheets are wrong and should be updated > [1] GXBB v1.1.4 > [2] GXL v0.3_20170314 > > Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") > Tested-by: Xingyu Chen > Signed-off-by: Yixun Lan > --- Applied fixes/drivers Thanks