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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fcaab2e0dsm433138266b.18.2026.02.18.02.43.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Feb 2026 02:43:30 -0800 (PST) Message-ID: <1511d067-6ee5-4be2-83c0-31775564a4c8@oss.qualcomm.com> Date: Wed, 18 Feb 2026 11:43:28 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 To: Sushrut Shree Trivedi , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20260212-industrial-mezzanine-pcie-v3-0-1e152937a76a@oss.qualcomm.com> <20260212-industrial-mezzanine-pcie-v3-2-1e152937a76a@oss.qualcomm.com> <97af21d5-7457-4dc1-bd47-2e34e6df094e@oss.qualcomm.com> <5c17f64e-5125-4365-b986-8c058cee292f@oss.qualcomm.com> <544be6af-fe02-425c-9457-4101f5dee80f@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <544be6af-fe02-425c-9457-4101f5dee80f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=eYAwvrEH c=1 sm=1 tr=0 ts=699597d4 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=-urqcF4WjNzwnZZbpCoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE4MDA5NSBTYWx0ZWRfX6rtZXlRQrk0P Rn/QrfkZVu7o3pYfEF60fOC6JfdFlVj+lo0on2lMdQ5sjpFoSp5vBhnbtjD6XItr8+XRwbWF9Zb iPqsVqc4DuBjoajourZ0xeqKosz93f2X8FnE2DtzO/ERVyg3CIK30mIU7yHgYPatDMPqNkMJfu7 lmzBjFu0xsMlZHSq4ZbeFsq85NjSNLSrPakYLjkKTa03WCwXmysHNnaPl87StpAAWi1BMAsKagK tW1ZCAntdbUem2yp6NoohdFC8g4jjlp1RzCl9oXUm1ybuQ0RVCQqLCnLu1UH6IUN1MBU5EipNXa RGcCc7cdz9enF1SHVBuE17ExfxCe7ETXD9bOsWIXvkpTfSCEgZBzBlAldZvPi7vzz80Ogswzy7B iB8ow2KnGGdPIR/tEydKlZdjKHWcSmrpWyYr/2QPDPNURnGXoTyVbu+dB8MSFk/JNB+HEg0SSyB MXXeN4jD8IlZnxX6Qsg== X-Proofpoint-GUID: axYI53hBGWVpj9bkXZBd8jHK23mVm8HN X-Proofpoint-ORIG-GUID: axYI53hBGWVpj9bkXZBd8jHK23mVm8HN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-18_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602180095 On 2/18/26 11:00 AM, Sushrut Shree Trivedi wrote: > > On 2/16/2026 4:58 PM, Konrad Dybcio wrote: >> On 2/15/26 3:19 PM, Sushrut Shree Trivedi wrote: >>> On 2/12/2026 5:16 PM, Konrad Dybcio wrote: >>>> On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote: >>>>> Add a node for the second TC9563 PCIe switch on PCIe1, which is connected >>>>> in cascade to the first TC9563 switch via the former's downstream port. >>>>> >>>>> Two embedded Ethernet devices are present on one of the downstream >>>>> ports of this second switch as well. All the ports present in the >>>>> node represent the downstream ports and embedded endpoints. >>>>> >>>>> The second TC9563 is powered up via the same LDO regulators as the first >>>>> one, and these can be controlled via two GPIOs, which are already present >>>>> as fixed regulators. This TC9563 can also be configured through I2C. >>>>> >>>>> Signed-off-by: Sushrut Shree Trivedi >>>>> --- >>>>> +&pcie1 { >>>>> +    iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, >>>>> +            <0x100 &apps_smmu 0x1c81 0x1>, >>>>> +            <0x208 &apps_smmu 0x1c84 0x1>, >>>>> +            <0x210 &apps_smmu 0x1c85 0x1>, >>>>> +            <0x218 &apps_smmu 0x1c86 0x1>, >>>>> +            <0x300 &apps_smmu 0x1c87 0x1>, >>>>> +            <0x408 &apps_smmu 0x1c90 0x1>, >>>>> +            <0x410 &apps_smmu 0x1c91 0x1>, >>>>> +            <0x418 &apps_smmu 0x1c92 0x1>, >>>>> +            <0x500 &apps_smmu 0x1c93 0x1>, >>>>> +            <0x600 &apps_smmu 0x1c94 0x1>, >>>>> +            <0x700 &apps_smmu 0x1c95 0x1>, >>>>> +            <0x701 &apps_smmu 0x1c96 0x1>, >>>>> +            <0x800 &apps_smmu 0x1c97 0x1>, >>>>> +            <0x900 &apps_smmu 0x1c98 0x1>, >>>>> +            <0x901 &apps_smmu 0x1c99 0x1>; >>>> This map is not just an extension of the existing one - is that >>>> intentional? >>> Yeah, I created a new map just for readability. Should I instead just add new mappings >>> and keep the older core-kit map intact ? >> Quite frankly, I don't know. I that against the "base" it's missing: >> >> 0x400 >> 0x501 >> >> so presumably the second DSP and an endpoint for the primary switch's >> ethernet port? > Since PCIe enumeration happens in a Depth-First Search manner, bus numbers > 3 to 7 are alloted to the cascade switch connected to DSP1 of primary switch. > Bus no.'s 8 and 9 are alloted to DSP2 endpoint and embedded ethernet EP > respectively, on the primary switch. > > So, in the cascade hierarchy, bus no. 4 is alloted to Cascade switch DSP's. > There is no DSP with device no. 0 so BDF 0x400 doesn't exist and is > omitted. For the same reason, BDF 0x200 on the primary switch is also > not mapped. > > BDF 0x501 in single switch case maps to the ethernet EP. In cascade, > that EP is being mapped to 0x901. OK, this is very useful to know, thank you Konrad