From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932581AbdLTT7V (ORCPT ); Wed, 20 Dec 2017 14:59:21 -0500 Received: from mga06.intel.com ([134.134.136.31]:28152 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932527AbdLTT7R (ORCPT ); Wed, 20 Dec 2017 14:59:17 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,433,1508828400"; d="scan'208";a="13971421" From: Sohil Mehta To: Joerg Roedel , Alex Williamson Cc: David Woodhouse , Ashok Raj , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jacob Pan , Gayatri Kammela , Sohil Mehta , Ravi V Shankar , Andy Shevchenko , Lu Baolu , Fenghua Yu , Kirill Shutemov , Dave Hansen Subject: [PATCH 4/4] iommu/vt-d: Enable 5-level paging mode in the PASID entry Date: Wed, 20 Dec 2017 11:59:27 -0800 Message-Id: <1513799967-22454-5-git-send-email-sohil.mehta@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513799967-22454-1-git-send-email-sohil.mehta@intel.com> References: <1513799967-22454-1-git-send-email-sohil.mehta@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the CPU has support for 5-level paging enabled and the IOMMU also supports 5-level paging then enable the 5-level paging mode for first- level translations - used when SVM is enabled. Signed-off-by: Sohil Mehta --- drivers/iommu/intel-svm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index 4072a18..d7095dd 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -26,6 +26,10 @@ #include #include +#define PASID_ENTRY_P BIT_ULL(0) +#define PASID_ENTRY_FLPM_5LP BIT_ULL(9) +#define PASID_ENTRY_SRE BIT_ULL(11) + static irqreturn_t prq_event_thread(int irq, void *d); struct pasid_entry { @@ -297,6 +301,7 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ struct intel_svm_dev *sdev; struct intel_svm *svm = NULL; struct mm_struct *mm = NULL; + u64 pasid_entry_val; int pasid_max; int ret; @@ -403,9 +408,15 @@ int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ kfree(sdev); goto out; } - iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1; + pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P; } else - iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11); + pasid_entry_val = (u64)__pa(init_mm.pgd) | + PASID_ENTRY_P | PASID_ENTRY_SRE; + if (cpu_feature_enabled(X86_FEATURE_LA57)) + pasid_entry_val |= PASID_ENTRY_FLPM_5LP; + + iommu->pasid_table[svm->pasid].val = pasid_entry_val; + wmb(); /* In caching mode, we still have to flush with PASID 0 when * a PASID table entry becomes present. Not entirely clear -- 2.7.4