From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752901AbdLULRZ (ORCPT ); Thu, 21 Dec 2017 06:17:25 -0500 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:49942 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752404AbdLULRW (ORCPT ); Thu, 21 Dec 2017 06:17:22 -0500 From: Matt Redfearn To: Ralf Baechle , James Hogan CC: , Matt Redfearn , "James Hogan" , "stable # v4 . 9+" , Huacai Chen , , Paul Burton Subject: [PATCH 2/3] MIPS: Add barrier between dcache & icache flushes Date: Thu, 21 Dec 2017 11:16:03 +0000 Message-ID: <1513854965-3880-2-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513854965-3880-1-git-send-email-matt.redfearn@mips.com> References: <1513854965-3880-1-git-send-email-matt.redfearn@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] X-BESS-ID: 1513855027-637138-12442-58568-10 X-BESS-VER: 2017.16-r1712182224 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.188217 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Index-based cache operations may be arbitrarily reordered by out of order CPUs. Thus code which writes back the dcache & then invalidates the icache using indexed cache ops must include a barrier between operating on the 2 caches in order to prevent the scenario in which: - icache invalidation occurs. - icache fetch occurs, due to speculation. - dcache writeback occurs. If the above were allowed to happen then the icache would contain stale data. Forcing the dcache writeback to complete before the icache invalidation avoids this. Similarly, the MIPS CM version 2 and above serialises D->I hit-based cache operations to the same address, but older CMs and systems without a MIPS CM do not and require the same barrier to ensure ordering. To ensure these conditions, always enforce a barrier between D and I cache operations. Suggested-by: Leonid Yegoshin Suggested-by: Paul Burton Signed-off-by: Matt Redfearn Cc: James Hogan Cc: stable # v4.9+ --- arch/mips/mm/c-r4k.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index ce7a54223504..b7186d47184b 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -741,6 +741,9 @@ static inline void __local_r4k_flush_icache_range(unsigned long start, else blast_dcache_range(start, end); } + + /* Ensure dcache operation has completed */ + mb(); } if (type == R4K_INDEX || -- 2.7.4