From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753033AbdLULRq (ORCPT ); Thu, 21 Dec 2017 06:17:46 -0500 Received: from 9pmail.ess.barracuda.com ([64.235.154.211]:38440 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751389AbdLULRp (ORCPT ); Thu, 21 Dec 2017 06:17:45 -0500 From: Matt Redfearn To: Ralf Baechle , James Hogan CC: , Matt Redfearn , "Paul Burton" , James Hogan , "stable # v4 . 9+" , Huacai Chen , Subject: [PATCH 3/3] MIPS: Add barrier between icache flush and execution hazard barrier Date: Thu, 21 Dec 2017 11:16:04 +0000 Message-ID: <1513854965-3880-3-git-send-email-matt.redfearn@mips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513854965-3880-1-git-send-email-matt.redfearn@mips.com> References: <1513854965-3880-1-git-send-email-matt.redfearn@mips.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.150.130.83] X-BESS-ID: 1513855054-321459-23116-47110-7 X-BESS-VER: 2017.16-r1712182224 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.188216 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hit-based icache operations may complete before the CM completes intervention with the local L1. Thus code which invalidates the icache and then attempts to execute those addresses must include a barrier to prevent the scenario which: - icache instruction completes - icache fetch occurs - core executes icache data - CM completes icache invalidate If the above were allowed to happen then the core would execute stale instructions from the icache. A barrier is required to prevent the core i-fetching before the icache operation has completed. This goes together with the instruction_hazard to ensure that the pipeline is stalled until the icache operation is completed and the core will fetch the new instructions. Suggested-by: Leonid Yegoshin Signed-off-by: Matt Redfearn Cc: Paul Burton Cc: James Hogan Cc: stable # v4.9+ --- arch/mips/mm/c-r4k.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index b7186d47184b..844685e51109 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -763,6 +763,8 @@ static inline void __local_r4k_flush_icache_range(unsigned long start, break; } } + /* Ensure icache operation has completed */ + mb(); /* Hazard to force new i-fetch */ instruction_hazard(); } -- 2.7.4