From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755254AbeAHCTM (ORCPT + 1 other); Sun, 7 Jan 2018 21:19:12 -0500 Received: from vern.gendns.com ([206.190.152.46]:51138 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755229AbeAHCTH (ORCPT ); Sun, 7 Jan 2018 21:19:07 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 29/44] ARM: da8xx: add new USB PHY clock init using common clock framework Date: Sun, 7 Jan 2018 20:17:28 -0600 Message-Id: <1515377863-20358-30-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: This adds the new USB PHY clock init in mach-davinci/usb-da8xx.c using the new common clock framework drivers. The #ifdefs are needed to prevent compile errors until the entire ARCH_DAVINCI is converted. Signed-off-by: David Lechner --- arch/arm/mach-davinci/usb-da8xx.c | 84 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index d480a02..d7340670 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -2,28 +2,36 @@ /* * DA8xx USB */ +#include #include +#include +#include #include #include #include #include +#include #include #include #include #include -#include #include #include #include #include +#ifndef CONFIG_COMMON_CLK +#include #include "clock.h" +#endif #define DA8XX_USB0_BASE 0x01e00000 #define DA8XX_USB1_BASE 0x01e25000 +#ifndef CONFIG_COMMON_CLK static struct clk *usb20_clk; +#endif static struct platform_device da8xx_usb_phy = { .name = "da8xx-usb-phy", @@ -128,6 +136,7 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata) return platform_device_register(&da8xx_usb11_device); } +#ifndef CONFIG_COMMON_CLK static struct clk usb_refclkin = { .name = "usb_refclkin", .set_rate = davinci_simple_set_rate, @@ -354,3 +363,76 @@ int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin) return ret; } +#else +/** + * da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock + * + * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true + * or "pll0_aux_clk" if false. + */ +int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin) +{ + struct regmap *cfgchip; + struct clk *usb0_psc_clk, *clk; + struct clk_hw *parent; + + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); + if (IS_ERR(cfgchip)) + cfgchip = syscon_regmap_lookup_by_pdevname("syscon"); + if (IS_ERR(cfgchip)) + return PTR_ERR(cfgchip); + + usb0_psc_clk = clk_get_sys("musb-da8xx", NULL); + if (IS_ERR(usb0_psc_clk)) + return PTR_ERR(usb0_psc_clk); + + clk = da8xx_usb0_phy_clk_register("usb0_phy_clk", "usb_refclkin", + "pll0_aux_clk", usb0_psc_clk, cfgchip); + if (IS_ERR(clk)) { + clk_put(usb0_psc_clk); + return PTR_ERR(clk); + } + + parent = clk_hw_get_parent_by_index(__clk_get_hw(clk), + use_usb_refclkin ? 0 : 1); + if (parent) + clk_set_parent(clk, parent->clk); + else + pr_warn("%s: Failed to find parent clock\n", __func__); + + return clk_register_clkdev(clk, "usb20_phy", "da8xx-usb-phy"); +} + +/** + * da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock + * + * @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true + * or "usb0_phy_clk" if false. + */ +int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin) +{ + struct regmap *cfgchip; + struct clk *clk; + struct clk_hw *parent; + + cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); + if (IS_ERR(cfgchip)) + cfgchip = syscon_regmap_lookup_by_pdevname("syscon"); + if (IS_ERR(cfgchip)) + return PTR_ERR(cfgchip); + + clk = da8xx_usb1_phy_clk_register("usb1_phy_clk", "usb0_phy_clk", + "usb_refclkin", cfgchip); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + parent = clk_hw_get_parent_by_index(__clk_get_hw(clk), + use_usb_refclkin ? 1 : 0); + if (parent) + clk_set_parent(clk, parent->clk); + else + pr_warn("%s: Failed to find parent clock\n", __func__); + + return clk_register_clkdev(clk, "usb11_phy", "da8xx-usb-phy"); +} +#endif -- 2.7.4