From: Will Deacon <will.deacon@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org,
marc.zyngier@arm.com, lorenzo.pieralisi@arm.com,
christoffer.dall@linaro.org, linux-kernel@vger.kernel.org,
shankerd@codeaurora.org, jnair@caviumnetworks.com,
Will Deacon <will.deacon@arm.com>
Subject: [PATCH v3 05/13] drivers/firmware: Expose psci_get_version through psci_ops structure
Date: Mon, 8 Jan 2018 17:32:30 +0000 [thread overview]
Message-ID: <1515432758-26440-6-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com>
Entry into recent versions of ARM Trusted Firmware will invalidate the CPU
branch predictor state in order to protect against aliasing attacks.
This patch exposes the PSCI "VERSION" function via psci_ops, so that it
can be invoked outside of the PSCI driver where necessary.
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
drivers/firmware/psci.c | 2 ++
include/linux/psci.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index d687ca3d5049..8b25d31e8401 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -496,6 +496,8 @@ static void __init psci_init_migrate(void)
static void __init psci_0_2_set_functions(void)
{
pr_info("Using standard PSCI v0.2 function IDs\n");
+ psci_ops.get_version = psci_get_version;
+
psci_function_id[PSCI_FN_CPU_SUSPEND] =
PSCI_FN_NATIVE(0_2, CPU_SUSPEND);
psci_ops.cpu_suspend = psci_cpu_suspend;
diff --git a/include/linux/psci.h b/include/linux/psci.h
index bdea1cb5e1db..6306ab10af18 100644
--- a/include/linux/psci.h
+++ b/include/linux/psci.h
@@ -26,6 +26,7 @@ int psci_cpu_init_idle(unsigned int cpu);
int psci_cpu_suspend_enter(unsigned long index);
struct psci_operations {
+ u32 (*get_version)(void);
int (*cpu_suspend)(u32 state, unsigned long entry_point);
int (*cpu_off)(u32 state);
int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
--
2.1.4
next prev parent reply other threads:[~2018-01-08 17:43 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-08 17:32 [PATCH v3 00/13] arm64 kpti hardening and variant 2 workarounds Will Deacon
2018-01-08 17:32 ` [PATCH v3 01/13] arm64: use RET instruction for exiting the trampoline Will Deacon
2018-01-08 17:32 ` [PATCH v3 02/13] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry Will Deacon
2018-01-09 17:17 ` Christoph Hellwig
2018-01-10 19:26 ` Will Deacon
2018-01-08 17:32 ` [PATCH v3 03/13] arm64: Take into account ID_AA64PFR0_EL1.CSV3 Will Deacon
2018-01-08 17:32 ` [PATCH v3 04/13] arm64: cpufeature: Pass capability structure to ->enable callback Will Deacon
2018-01-08 17:32 ` Will Deacon [this message]
2018-01-08 17:32 ` [PATCH v3 06/13] arm64: Move post_ttbr_update_workaround to C code Will Deacon
2018-01-08 17:32 ` [PATCH v3 07/13] arm64: Add skeleton to harden the branch predictor against aliasing attacks Will Deacon
2018-01-09 12:55 ` Philippe Ombredanne
2018-01-08 17:32 ` [PATCH v3 08/13] arm64: KVM: Use per-CPU vector when BP hardening is enabled Will Deacon
2018-01-08 17:32 ` [PATCH v3 09/13] arm64: KVM: Make PSCI_VERSION a fast path Will Deacon
2018-01-08 17:32 ` [PATCH v3 10/13] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Will Deacon
2018-01-08 17:32 ` [PATCH v3 11/13] arm64: Implement branch predictor hardening for affected Cortex-A CPUs Will Deacon
2018-01-09 16:12 ` Suzuki K Poulose
2018-01-15 11:51 ` Marc Zyngier
2018-01-15 18:01 ` Catalin Marinas
2018-01-08 17:32 ` [PATCH v3 12/13] arm64: Implement branch predictor hardening for Falkor Will Deacon
2018-01-12 17:58 ` Shanker Donthineni
2018-01-08 17:32 ` [PATCH v3 13/13] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Will Deacon
2018-01-08 18:53 ` [PATCH v3 00/13] arm64 kpti hardening and variant 2 workarounds Catalin Marinas
2018-01-09 14:07 ` Matthias Brugger
2018-01-12 15:58 ` Catalin Marinas
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