From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2244WFcy6n51Fs83Rk7Ak54Hd8ExVegjvJtc9t+S2b5lKPTUz/a1DZsC6idJ263CcXi4gBPn ARC-Seal: i=1; a=rsa-sha256; t=1516449840; cv=none; d=google.com; s=arc-20160816; b=h0pNhHGhMcM9rBYBQQ9L16QhkeDsZDP7wiHNGrvXlwPwN3Mfe5DFSZlx9bqLYLOrIU a9M6h928a9b7xDP+d2A88wTSziHxXMUTK3iSFP4WV3KwPmdtI/Y0eiHw4M2c3l1SMs0X xJkxoFPVjYgJE6EaczHIkj8jdT22K/HlnFD9LXOuQ6OWtVVCVkr6aUl8LzhI1nwqNC54 5yci7vP63LJzrMoxIiI7l4Rt5F0O/81vfZrrDveDxQsHfyCQ+neLrA+vGhXQ2UqaZbrP cumugbVIoHYQsTO/wl8zNJl6XpiqpJNdtC6wHxwwx8CY+G3oYMZrS1HkP+YJ3zpxiZ8M Roxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=CdYCXE1QF47JHZJuEjUSXWDmGKL52VQvNlTffXpDST8=; b=Z9MPVb8Fdws2RVgoU6upXmoP+T9nTewqlXG5hjVrQOwGaDudGHc9RPIlfJcSP05S+i 5DCBpHafJO238VNFDojm5HxH/NElJzJsjVMsntHCXQOrvULsa0cVn2o0JH2mLud2Y1bD FUujTsf/KoehiwXY3bElVtGYOTgwLDPlS4o/vu9YruV6dJ6No15IlKFC+ZA9trYzTu0D tpg8/wjAxqQzrT1l1vS8TZADZDAHd4+EnacYB1dGyMdkUPm2u9tQunoaPhx/UL+3LsZ2 gjDw3Xhrff6bJ4YaZYJTNXXftnYyT8IbOJ3xfkuR90ndJCizB5cSLKSFs5BMCq3gORZj gx8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=du4bekQE; spf=pass (google.com: domain of prvs=55101727d=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=55101727d=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=du4bekQE; spf=pass (google.com: domain of prvs=55101727d=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=55101727d=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,386,1511827200"; d="scan'208";a="704460039" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: [PATCH 2/4] x86/cpufeatures: Add AMD feature bits for Prediction Command Date: Sat, 20 Jan 2018 12:03:31 +0000 Message-Id: <1516449813-7654-3-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590112908013365211?= X-GMAIL-MSGID: =?utf-8?q?1590112908013365211?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: AMD doesn't implement the Speculation Control MSR that Intel does, but the Prediction Control MSR does exist and is advertised by a separate CPUID bit. Add support for that. Signed-off-by: David Woodhouse --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index adebdaa..624d978 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -207,6 +207,7 @@ #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index df11f5d..c76009e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, + { X86_FEATURE_AMD_PRED_CMD, CPUID_EDX, 12, 0x80000007, 0 }, { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, { 0, 0, 0, 0, 0 } }; -- 2.7.4