From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2240FftoMDkRGJBU7EuvOAA+hTCGAghL6Vd7EJ/GZKyaVmjb8g8dAzDhW7/vNxUuAlLhdlQR ARC-Seal: i=1; a=rsa-sha256; t=1516449966; cv=none; d=google.com; s=arc-20160816; b=BjfQ7QkcAp2u0JUQP9p5/IzHpSP+ssaPJJUyrYWr8n2jCAyK7mrWzEjqdes3kam0DX kMbS/oAYUeHZpgDXAgPLJCc0MJQWhHQAXNahZS2vOOllQFzhjajUYOMm7YJqup9uN/80 ficBKFoCF9upaakiYoAo5sjeO2mO845CSgfP0OvdLWl6u50MWzdYMQCVbFc8qN15tt+G 41mqg+LzqET5hSmdOM/T6KxABR45JyU5OFIBMne0JGICL9U9Q7I1DRZmaXIBfgUqG6OF L/C4P46aD/CoExmcfa+kqnHl6N+Oe27oEj61pjIAUkjBg1AGte4UYgPWU+2rXDzl7nm3 al6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=dbbv01J6xXxsDJfWqdDlVzSm4ezB0L1/oPxaBGvI8us=; b=BiHgaqZc40aiJMgJJVRmBdvshTOooX/gyj6+t+oLw7D4o8UslPt/QlUW9XyuuDcr1d eR5ZA2of0fPfZveWQtvN+lhyHHSJOaQBS72clEQMyIGYHEGw4NAMOKttKeDE8VM4BO1z gW4zUsfwLmIrP7q0j4dDbBT9g18Ozse7K+w4nZj4qr9YnMowD3ni6jhv9mQEIpo8TUmP 410/f03mp3GKPsdhE6PQ7t9HYr9rOhbJgT+R54HjlKPcL+3F3np+0baQxDBxvIbNH4tS YTzjHiBNCNS3eTJokVsv/0t9Db88ripe0ELNyV7VEhd06nUjcVzkf2ZsN4V2jnV8TGXa lmlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=Hd++heBd; spf=pass (google.com: domain of prvs=55101727d=dwmw@amazon.com designates 207.171.184.25 as permitted sender) smtp.mailfrom=prvs=55101727d=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=Hd++heBd; spf=pass (google.com: domain of prvs=55101727d=dwmw@amazon.com designates 207.171.184.25 as permitted sender) smtp.mailfrom=prvs=55101727d=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,386,1511827200"; d="scan'208";a="720475845" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: [PATCH 3/4] x86/msr: Add definitions for new speculation control MSRs Date: Sat, 20 Jan 2018 12:03:32 +0000 Message-Id: <1516449813-7654-4-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590113039684486151?= X-GMAIL-MSGID: =?utf-8?q?1590113039684486151?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES. See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: David Woodhouse --- arch/x86/include/asm/msr-index.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index fa11fb1..c37fafa 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -42,6 +42,13 @@ #define MSR_PPIN_CTL 0x0000004e #define MSR_PPIN 0x0000004f +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ +#define SPEC_CTRL_STIPB (1 << 1) /* Single Thread Indirect Branch Predictors */ + +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ + #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd @@ -60,6 +67,10 @@ #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ + #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176 -- 2.7.4