From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x227QvqfLI7Qjwcai5oddOoEsuVgfnkMF81sKyezBn38s0BOYfMTV/692Ad/XDZR6ck52Pg+l ARC-Seal: i=1; a=rsa-sha256; t=1516528168; cv=none; d=google.com; s=arc-20160816; b=WGjRoi0irQvHbrY5feSUEYiM3mVGijdnQ25SKOj/RTKYLm4oXnZjytDkwyowDZVmh9 K9rNMbu5UmgU8OUhlfp2XzlXNrL+Jynmmcep8zqYfkNxUmQRzPwipExY3U+KyRxiqFuk JX64lzxSyqhfkTa5s6sQMiQcLuFke3U9JzaV2lOvAKHzcdCICHzNhusDjvud1cXCY/NQ HFixznWGs6BJrnrRS852w0CXZsIcba6fXti8r6z/f2IixiRW4po4jS4OBCZo+ZR3VlkN JhfSn+6yEn94ci/PwcnjAANgGRsHNK8QdhVFuy8UNmE8m/7J/robOpzHSSEhCgZY7GWG DsDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=zSjXczCLziDF+GesyIl9wihkLDbbV5Ew1M/RCmmsqig=; b=PR8VHPOocSdooODdYXMx5y5cIq1SZeXQuX4WtVKasAgEXk7ix8FugUK95nombYSh9W etQmDqlf06CMGeE2TLUsKIVMIqnz+BhGaKzOvtBdWCI/8hOjez8+KEAqUjHb/pwNZ/QV M9XNSY40DUxQCPKYvlyo7p0+dHgfPseECjOU72XYioEDUc6P6eIzKMJXx8w/8aONJhAr O7q4GDRywPOdhVLmenAvpXUxZLrmX7F640zi2qpiQdJTeB9oac6JR2PvWx0Bed7dEZXZ ZUJxvsxMrEggNwgN+7qRRjI4hMAPia5Uy5qwFCGUzBFxhNyaVz2OMdlP4xgfsg1rhvqg FZAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=eH675+YQ; spf=pass (google.com: domain of prvs=552b621e3=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=552b621e3=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=eH675+YQ; spf=pass (google.com: domain of prvs=552b621e3=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=552b621e3=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,390,1511827200"; d="scan'208";a="588471097" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: [PATCH v2 2/8] x86/cpufeatures: Add AMD feature bits for Prediction Command Date: Sun, 21 Jan 2018 09:49:03 +0000 Message-Id: <1516528149-9370-3-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195040636439803?= X-GMAIL-MSGID: =?utf-8?q?1590195040636439803?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: AMD doesn't implement the Speculation Control MSR that Intel does, but the Prediction Control MSR does exist and is advertised by a separate CPUID bit. Add support for that. Signed-off-by: David Woodhouse --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2efb8d4..8c9e5c0 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -207,6 +207,7 @@ #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR (AMD) */ #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index df11f5d..4eb90b2 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, + { X86_FEATURE_AMD_PRED_CMD, CPUID_EBX, 12, 0x80000008, 0 }, { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, { 0, 0, 0, 0, 0 } }; -- 2.7.4