From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226VhmzHrbgji1l13zO7QX+9OfouCJcMyN+TlzDa7rekwLRWbAaR18O+9pxOPv5i3EEpht/a ARC-Seal: i=1; a=rsa-sha256; t=1516528179; cv=none; d=google.com; s=arc-20160816; b=N2xNjKwV6oqVhwOlHRfTQElrdAFJr6j19qMb0Cn9mD9+qFznK2MchZX34F/hFAmJGB PuTDalSHFyjWjPfeLakusVy8jcf7wXx1SPpcbVFRvO6fB7qDf5qLm5KZukPAYFdT7q/6 vi6xFDdS60CLVVbLJtDAdv0nwXaK1z/VsJuJViwKA//WSg7LBU6DeQg14AibmlwLWZkJ kotwk4vRbqK3eMVBOSbDh/BwPMzGogfgNFuq4Cr9JmJaDM34fTzzjk9Bwk7rxjYjoKVz 4QPJhUAfKgO5Il9ziEACEROLovsIZQ7rsZd3FkAOLIds/AhnvpM3039imdTe1SE0GNku yevg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=wncma6E3YRn59Z0//+y71jG96FxClgiDvLwQN01BxrI=; b=RSi4+NiSsJqge5vTy7OmG2eZzehfcoiG2k8z35I9wRgvYUod6Q/BcvV7g24JMh1ff7 VuvGuLJcSXtDlcghqlJ0O5GgNClYjSU8lTv6Ct2M+YrA6Up5C+bU7x6XYWnkMiTbpbWi KCiRaRsh6bXGT+4kQoZYeQbcSmQXuwZbBUO3ySXgXUq02DMbH1bzbG7VF8h1DV0BMWQk 3ZlghyD+9oHDfe4Byu90I7aujHpWPUIpydjS/mqeBxllA3CwS0tMn2StcNDRY9LBOaJ7 FX6/gvV/gx/UQjfowtGzM1AgS0UlDjNFuh2dl8TQGdciCzy/yGru1CZL4NyzG2MTxOei LVEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=DLj1jn8z; spf=pass (google.com: domain of prvs=552b621e3=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=552b621e3=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=DLj1jn8z; spf=pass (google.com: domain of prvs=552b621e3=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=552b621e3=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,390,1511827200"; d="scan'208";a="704575207" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: [PATCH v2 6/8] x86/kvm: Add IBPB support Date: Sun, 21 Jan 2018 09:49:07 +0000 Message-Id: <1516528149-9370-7-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195053086080649?= X-GMAIL-MSGID: =?utf-8?q?1590195053086080649?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Ashok Raj Add MSR passthrough for MSR_IA32_PRED_CMD and place branch predictor barriers on switching between VMs to avoid inter VM specte-v2 attacks. [peterz: rebase and changelog rewrite] [karahmed: - vmx: expose PRED_CMD whenever it is available - svm: only pass through IBPB if it is available] [dwmw2: - vmx: allow X86_FEATURE_AMD_PRED_CMD too] Cc: Asit Mallick Cc: Dave Hansen Cc: Arjan Van De Ven Cc: Tim Chen Cc: Linus Torvalds Cc: Andrea Arcangeli Cc: Andi Kleen Cc: Thomas Gleixner Cc: Dan Williams Cc: Jun Nakajima Cc: Andy Lutomirski Cc: Greg KH Cc: Paolo Bonzini Signed-off-by: Ashok Raj Signed-off-by: Peter Zijlstra (Intel) Link: http://lkml.kernel.org/r/1515720739-43819-6-git-send-email-ashok.raj@intel.com Signed-off-by: David Woodhouse Signed-off-by: KarimAllah Ahmed --- arch/x86/kvm/svm.c | 14 ++++++++++++++ arch/x86/kvm/vmx.c | 11 +++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 2744b973..cfdb9ab 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -529,6 +529,7 @@ struct svm_cpu_data { struct kvm_ldttss_desc *tss_desc; struct page *save_area; + struct vmcb *current_vmcb; }; static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); @@ -918,6 +919,9 @@ static void svm_vcpu_init_msrpm(u32 *msrpm) set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); } + + if (boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) + set_msr_interception(msrpm, MSR_IA32_PRED_CMD, 1, 1); } static void add_msr_offset(u32 offset) @@ -1706,11 +1710,17 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu) __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); kvm_vcpu_uninit(vcpu); kmem_cache_free(kvm_vcpu_cache, svm); + /* + * The vmcb page can be recycled, causing a false negative in + * svm_vcpu_load(). So do a full IBPB now. + */ + indirect_branch_prediction_barrier(); } static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { struct vcpu_svm *svm = to_svm(vcpu); + struct svm_cpu_data *sd = per_cpu(svm_data, cpu); int i; if (unlikely(cpu != vcpu->cpu)) { @@ -1739,6 +1749,10 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (static_cpu_has(X86_FEATURE_RDTSCP)) wrmsrl(MSR_TSC_AUX, svm->tsc_aux); + if (sd->current_vmcb != svm->vmcb) { + sd->current_vmcb = svm->vmcb; + indirect_branch_prediction_barrier(); + } avic_vcpu_load(vcpu, cpu); } diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index d1e25db..1e45bb3 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2279,6 +2279,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; vmcs_load(vmx->loaded_vmcs->vmcs); + indirect_branch_prediction_barrier(); } if (!already_loaded) { @@ -6791,6 +6792,16 @@ static __init int hardware_setup(void) kvm_tsc_scaling_ratio_frac_bits = 48; } + /* + * The AMD_PRED_CMD bit might be exposed by hypervisors on Intel + * chips which only want to expose PRED_CMD to guests and not + * SPEC_CTRL. Because PRED_CMD is one-shot write-only, while + * PRED_CMD requires storage, live migration support, etc. + */ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) || + boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) + vmx_disable_intercept_for_msr(MSR_IA32_PRED_CMD, false); + vmx_disable_intercept_for_msr(MSR_FS_BASE, false); vmx_disable_intercept_for_msr(MSR_GS_BASE, false); vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); -- 2.7.4