From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x225u46KNO84j1M3PJDIeNmb00Yc/pqTxhOfEQNM07gfJ1HG08vWtw0LjLSeX7xyeTqLcLzHL ARC-Seal: i=1; a=rsa-sha256; t=1516819112; cv=none; d=google.com; s=arc-20160816; b=vYjFJ6gyoN6KH+C1RyJZVFom8BSwymaePCibDThvZE1d/WOCRo0hF/K7ZYPomrUJva Ow9LwD9ttqfZ1qLgBIxVLaKn5ycpia0g6i7dOQt2oK5rhqdpaCCY30BCvc5clUIVexM5 uIn9CdU/xyu1ekKTQmjU+PPtk7NmOLyZlOmlsS/egXD8eJ+daKPtg15RGWUm9mz65+9q b25W3/u/WWPHb/cBFdwGF9iEG5zX5VIH72XwF6GqNW+OjNVK7UhV7sy5URFAJTnUWBw/ zj3+A53dv6XJTLhNNhWyuqKJ4em+axLaIvLUGe5rrA4yZ8UIZpKjB3WS87I3yxaCE9mO Z00Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=IjDy3yYvlmxTmTck12HjaXeWmqb8qI78ubWf/G029kc=; b=UEot24pF5Y/1wbHyQrp+Eih2xjfVElizq7e8uLyOuqNIVeTq8z/hjaCjGGCI+4ljaQ xX3fqMej+PUQkf4PtifsRcRvQv0sXE28jydtvL7VR3YAnu0Ey5Hbuc5xuUCJhCH2XeKK oK3h2szcjQ0oy5I+/bqVEO4ZYv9UKLmnSr8O2MO645rRq+6rPy4SfVz5dG6PlgwAb4ky TxzXCtTP1bigWlQdrxDWMHqg6VITr37Q8Pdl2sbXlqNYKl6V09+7ySIUOuDhArP2nyXn wJFGI9gbBzXLXtcRKWfUeFzDOAhGZAPaGqXhoQIOKADfCPcmR7aY8N/nR+qUUEkz2kWR wD+A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of vadimp@mellanox.com designates 193.47.165.129 as permitted sender) smtp.mailfrom=vadimp@mellanox.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=mellanox.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of vadimp@mellanox.com designates 193.47.165.129 as permitted sender) smtp.mailfrom=vadimp@mellanox.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=mellanox.com From: Vadim Pasternak To: dvhart@infradead.org, andy.shevchenko@gmail.com, gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, jiri@resnulli.us, Vadim Pasternak Subject: [patch v11 10/12] platform/x86: mlx-platform: Extend register map configuration with IO access verification callbacks Date: Wed, 24 Jan 2018 20:34:56 +0000 Message-Id: <1516826098-125036-2-git-send-email-vadimp@mellanox.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1516826098-125036-1-git-send-email-vadimp@mellanox.com> References: <1516826098-125036-1-git-send-email-vadimp@mellanox.com> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590500118381184352?= X-GMAIL-MSGID: =?utf-8?q?1590500118381184352?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add definitions for hotplug device masks and events offsets. Extend register map configuration with the sets of writable, readable and volatile registers to allow verification prior to the access. Extend register map configuration with cache type field: use flat type. Signed-off-by: Vadim Pasternak --- drivers/platform/x86/mlx-platform.c | 71 +++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 81a7306..95eb9d9 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -48,9 +48,18 @@ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a +#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b +#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 +#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 +#define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 +#define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 +#define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 +#define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 +#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 +#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda @@ -299,6 +308,64 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, }; +static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + return true; + } + return false; +} + +static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + return true; + } + return false; +} + +static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: + return true; + } + return false; +} + static int mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) { @@ -317,6 +384,10 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config = { .reg_bits = 8, .val_bits = 8, .max_register = 255, + .cache_type = REGCACHE_FLAT, + .writeable_reg = mlxplat_mlxcpld_writeable_reg, + .readable_reg = mlxplat_mlxcpld_readable_reg, + .volatile_reg = mlxplat_mlxcpld_volatile_reg, .reg_read = mlxplat_mlxcpld_reg_read, .reg_write = mlxplat_mlxcpld_reg_write, }; -- 2.1.4