From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x22526zmQZdkAtJ5ASqCdehITT5T/vTUvE7rjIHJayy5YQNkYZUbpwkZNXptYf9/sWIWhl0b3 ARC-Seal: i=1; a=rsa-sha256; t=1516872233; cv=none; d=google.com; s=arc-20160816; b=Sw51yCy9tT7ylknvNzUklK6AejJFm6ObY+ZLOMeZp46HRMj3XpJE4xfPPJBwLuMu2N C45X8uVVvPMvet0BOPFMt06I4m/nsGvBnjCl/s/KFhmvKNlr43Nr1eMSW/xUXY3b5duN XkcJhA3qbHJN2jFSfpoJY5NCxtbEecJdpJ6UiumDu0E8pliampRC4X1NqREy64impOM2 dv5M11WdQiWL4wR4Nw01Nu87Ty3+UhKY6IcVFPV+Er6GhMSLeRcnYJbhM+s5Vn5XyYae 7rb9Mcrhu55mkphMWhXG1EuYUJwYfYZzHVJf/KUjgEe3pD40L43jsCFA8uQynLzaeknV DTlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=C4k0L+16qv9f8gu34YJZS5nqCBs+ElTbJMSmTxfZrzg=; b=JfJszMPtIYIzI8tp2KmFrwli1vsbw1MhQ7LLOyOhhlAXswlCPYCGzUD1OezdKpTHXr GPmgeeZCHUwN7PKkPOHsWObinpPeW1N9/JlMK2EnDxcz+Vwd7I7qKS8MeNOQXm0C7CEd ukCfDwNC2W/o6qVjNxzi4oCYxJqfZR9a5oZkXMe1ON1rOzJSw45Tp4vzVdKcSEQcW7nM yH/QRVDnAhnPZ6ypnp94MepBatWqOWSFMTNA/EHFPVpBeWwGc4ydBEp8r/jvS7+ObHN1 rKQgCeTsPTL7eiCHDzhoF1S+E86uNfnYU+YpC+unJe1dp81JWT1NoKBbFa4m77qmMpzH pvqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=vOQ71fDa; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=vOQ71fDa; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,411,1511827200"; d="scan'208";a="589777988" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v4 3/7] x86/cpufeatures: Add AMD feature bits for Speculation Control Date: Thu, 25 Jan 2018 09:23:05 +0000 Message-Id: <1516872189-16577-4-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555819438908618?= X-GMAIL-MSGID: =?utf-8?q?1590555819438908618?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@amd.com Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 0a51070..ae3212f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -269,6 +269,9 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR (AMD) */ +#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR only (AMD) */ +#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ -- 2.7.4