From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x227aJdlos9MSncgUs5qt9Il0cawqpOoBlf4eiDujvQQ+f+cqKvjyGiy7RHDw9Vn8M2HhHbMZ ARC-Seal: i=1; a=rsa-sha256; t=1516872248; cv=none; d=google.com; s=arc-20160816; b=vSj5NKBhy5zZ7zBygYQBFpBf4jilIW0Zm52RNAZtaMZAMRiRbEFU8JJK3hkOvue/ew X7qinW2f9gCTkhJucPMiXhj1v5VKjsr4PeHJBPytJP/GRBUUERf3++LkRAYXaNjKKDuG GUmuMkDUIJ6yLAnnYOxXSGhU04Hq1QdonUNIIaJqO4pW5UYkbskD1gMwjN9otgdw14cf HgBF1RorpRzzimuX4/+RopR64ZCsWwRStEtZi4gQcsNYS4BsZKFKgvc7dsg5bOT65k+j C8FlvS+UqMCsAEXyav4SnlvXZHKK0GqT7gdDKuSMLiWGBqv/x9jbZXnnkpEQqC6wyyt2 HqIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=GkhjsaMS5Bme/Ox+tx4JKBCYNXZocDfBtlXw8PoahO4=; b=ox+zFzevKD77sPecp8i6pWxOPsREoOkK8oOzhsCxFbmDc6U52+rPwNTBkz4Gx7d48T DxjSyoV6pEVVqva/7Y+VNqFNzKcze4RUtHBejjAQPgPF7P2inYPltwGBrFgyRIE1pkAD lgjabqp2cIwrUaaVufjWxZS/2LNjJC77e+D0VDdunuoA6nUbYVGXdJxxbRe1+sNNBSOI iHUR1GLhq8pa815E84jWX11PcXyPjIZw5PZp7NSkqZpDu4H4g46sOvEi6Xrx9irYuKXV Sfy0wDkDDw2qV4hzHntg4MCJf9LnZondnRnB1nIaC6nPBy0q4+yTy2kv2pe5yqOQ5yEW 8bIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=oVU0CNYc; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.190.10 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=oVU0CNYc; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.190.10 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,411,1511827200"; d="scan'208";a="717039830" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v4 4/7] x86/msr: Add definitions for new speculation control MSRs Date: Thu, 25 Jan 2018 09:23:06 +0000 Message-Id: <1516872189-16577-5-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555835178069748?= X-GMAIL-MSGID: =?utf-8?q?1590555835178069748?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES. See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman --- arch/x86/include/asm/msr-index.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index fa11fb1..eb83ff1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,13 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ + +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ + #define MSR_PPIN_CTL 0x0000004e #define MSR_PPIN 0x0000004f @@ -57,6 +64,11 @@ #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) #define MSR_MTRRcap 0x000000fe + +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ + #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e -- 2.7.4