From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224lKDMzaqdSDPxzvn9wZbe4oYZL039b6qEnB6bKwJBgKj0zziwhs6x9mgLR833wcq0wwx35 ARC-Seal: i=1; a=rsa-sha256; t=1516872259; cv=none; d=google.com; s=arc-20160816; b=zsSSLoOKzvK7J3/ACvA5VNJ0PDiN8qjRTACVHwPzACKdhHMRByaz6nh1EztqDfsyfO 2pFlOfNAw9P2LtGOQ2mb3wCl1C9+Ir9NwBE2ee5HfATAo5eCzALjOKpUG+bbqspGYKQA VwIYMW33MDGwQc5uX/vT4Ld7oM/TNi/vOJJlD3Ts+OOp5aCjcjPT/L3+3kIH0vyG/kGW hTW2o2hUaOcf4nwBs4FRPzZ42FO9T/FltLAuwHrHbd4hkEjh3wt18non6HaP5NWtU1B0 jKBOoxSayk9ao9cSMk0+skYHzWqAgNtafFS5ax0HtDVl/3IOUUCewf1xpFXKmWZ/AURy vJUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=ZvZYs7DuyLJi1L3TH4HgrayTl5EcH5bkgTyZypWHH/Q=; b=XyaYFh8+NnewBBIBFwMsWeWHd42kO/qdtfxbzPddQ3yg2ggm/z3j5vHjbwSGS2IzGO 2WMDKo4WjnMS667/XrvlNkRpe5Jkr5iSHBhb5GagXu4cfxQSoAu3CV/HEnYhk1UdN+Qf wWmD0tFXDb91RlxJq7IaFM+uJtO1VQH96j514CmpzClGjaBv21MpGt1ii+FyPuzrej8E o1MGiAaM8ZGfDdqUmx1EffJC6dCtGgcstzP+X7Z4t4cG8R4Gfea50s25BAtPS+M3SYy9 c/TSvsZY4EBHiRG9ARmMuK+hHEcY34ulSoTpZdU4MGo5f4yz6NvI7EDSCk2Sf/p40TEM cY1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=mKepDeil; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=mKepDeil; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 207.171.184.29 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,411,1511827200"; d="scan'208";a="589778044" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v4 5/7] x86/pti: Do not enable PTI on processors which are not vulnerable to Meltdown Date: Thu, 25 Jan 2018 09:23:07 +0000 Message-Id: <1516872189-16577-6-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555846213033818?= X-GMAIL-MSGID: =?utf-8?q?1590555846213033818?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Also, for CPUs which don't speculate at all, don't report that they're vulnerable to the Spectre variants either. Leave the cpu_no_meltdown[] match table with just X86_VENDOR_AMD in it for now, even though that could be done with a simple comparison, on the assumption that we'll have more to add. Based on suggestions from Dave Hansen and Alan Cox. Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/common.c | 47 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e5d66e9..08c3efb 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -47,6 +47,8 @@ #include #include #include +#include +#include #ifdef CONFIG_X86_LOCAL_APIC #include @@ -853,6 +855,40 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) #endif } +static const __initdata struct x86_cpu_id cpu_no_speculation[] = { + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, + { X86_VENDOR_INTEL, 5 }, + { X86_VENDOR_CENTAUR, 5 }, + { X86_VENDOR_ANY, 4 }, + {} +}; + +static const __initdata struct x86_cpu_id cpu_no_meltdown[] = { + { X86_VENDOR_AMD }, + {} +}; + +static bool __init early_cpu_vulnerable_meltdown(struct cpuinfo_x86 *c) +{ + u64 ia32_cap = 0; + + if (x86_match_cpu(cpu_no_meltdown)) + return false; + + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); + + /* Rogue Data Cache Load? No! */ + if (ia32_cap & ARCH_CAP_RDCL_NO) + return false; + + return true; +} + /* * Do minimum CPU detection early. * Fields really needed: vendor, cpuid_level, family, model, mask, @@ -900,11 +936,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) setup_force_cpu_cap(X86_FEATURE_ALWAYS); - if (c->x86_vendor != X86_VENDOR_AMD) - setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); - - setup_force_cpu_bug(X86_BUG_SPECTRE_V1); - setup_force_cpu_bug(X86_BUG_SPECTRE_V2); + if (!x86_match_cpu(cpu_no_speculation)) { + if (early_cpu_vulnerable_meltdown(c)) + setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); + setup_force_cpu_bug(X86_BUG_SPECTRE_V1); + setup_force_cpu_bug(X86_BUG_SPECTRE_V2); + } fpu__init_system(c); -- 2.7.4