From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x225+S1QG+/n8y+tiifPSL9Dt0XEvSz8tUVkNkzeX6wWTm3qjPdayZvio/sazQdUeATU3eRN8 ARC-Seal: i=1; a=rsa-sha256; t=1516872543; cv=none; d=google.com; s=arc-20160816; b=f5J00EuUdlcxo+3xm5m4rQfbdLV4QaDTfq2nW7PZAi67cLKrmDUO8fIR5fv6i6HhNS 59QsQU/nXU+RbkXWh94FsVatwT9Kci0Wvnl0A30DHlO7sD6m3kNaBAZQ3tqkyO6Zh2p/ /ACUhdqi8w6C3u2o8qSzX29uh8i63dC1kTO3GtBAXa30ZExFHDVhPtYCWcFXWujOWdUG Ay2F5sNMA2j1EzJu5wQP6DD5L+gUheq3xuq2qeVnJwV3dkR2IhgMSd3uaUz0cBE83ckZ 4GsdqRFXTA+iUjRYXrOOFBaBBOHeMfYRY37SHTjmMRVtZ1gPXsjtRYaMQAg0vxN0JyBA n/FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=i0PeowlGk0XvN6XSWgsIg/5drQvHp3sZL2ZFPCjjWek=; b=OB7pDPFjNPdlNLtTtcUsHHvLedhesPYjCxloEgZpWzeVKAwNQ9GqQrebaDNOY3ilSZ vEmKsmdH1AfAj2NKg80nSbqMKzIx/D5Yf1qDGnwoPLus6F7faZEwyX3t3NvwOW+nUkDS CRMcQXA/pb7IrViQdIuxla93fbTrC2OLkSboe7w6B9BDDqeeQXSBYJ5dlSy5+aeTPnJI bQwxgJxqPKZjkTuc6iepiHL4Kp5Xdns/Unlox/PnE41bylcx54oRfp8dQ8VJC9HMpd01 YZoskaytat+9NI9au+DWRhU2HRZFNMPeAiXFyaIM+FIrB9Fch5Dj98CHwhZdWzg7PtIS Irww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=ks6/o0NN; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.196.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=ks6/o0NN; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.196.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,411,1511827200"; d="scan'208";a="665851739" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v4 7/7] x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support Date: Thu, 25 Jan 2018 09:23:09 +0000 Message-Id: <1516872189-16577-8-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590556144645656370?= X-GMAIL-MSGID: =?utf-8?q?1590556144645656370?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Expose indirect_branch_prediction_barrier() for use in subsequent patches. [karahmed: remove the special-casing of skylake for using IBPB (wtf?), switch to using ALTERNATIVES instead of static_cpu_has] [dwmw2: set up ax/cx/dx in the asm too so it gets NOP'd out] Signed-off-by: Thomas Gleixner Signed-off-by: KarimAllah Ahmed Signed-off-by: David Woodhouse --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/nospec-branch.h | 13 +++++++++++++ arch/x86/kernel/cpu/bugs.c | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index ae3212f..6b988278 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -207,6 +207,7 @@ #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ +#define X86_FEATURE_IBPB ( 7*32+16) /* Using Indirect Branch Prediction Barrier */ #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 4ad4108..34e384c 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -218,5 +218,18 @@ static inline void vmexit_fill_RSB(void) #endif } +static inline void indirect_branch_prediction_barrier(void) +{ + asm volatile(ALTERNATIVE("", + "movl %[msr], %%ecx\n\t" + "movl %[val], %%eax\n\t" + "movl $0, %%edx\n\t" + "wrmsr", + X86_FEATURE_IBPB) + : : [msr] "i" (MSR_IA32_PRED_CMD), + [val] "i" (PRED_CMD_IBPB) + : "eax", "ecx", "edx", "memory"); +} + #endif /* __ASSEMBLY__ */ #endif /* __NOSPEC_BRANCH_H__ */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 390b3dc..96548ff 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -249,6 +249,13 @@ static void __init spectre_v2_select_mitigation(void) setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); pr_info("Filling RSB on context switch\n"); } + + /* Initialize Indirect Branch Prediction Barrier if supported */ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) || + boot_cpu_has(X86_FEATURE_AMD_PRED_CMD)) { + setup_force_cpu_cap(X86_FEATURE_IBPB); + pr_info("Enabling Indirect Branch Prediction Barrier\n"); + } } #undef pr_fmt -- 2.7.4