From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226a1TWUjN+l8pMciqqEM1f83kE7qDe7IuwK5fds2d+A+dKn+ZVFiiLoW77cDJad6qcjmp6K ARC-Seal: i=1; a=rsa-sha256; t=1516896876; cv=none; d=google.com; s=arc-20160816; b=A+Oqg7meTOma0unX+gQNwRn0dxjKMeNRh2tgzw0sRZ7LQ5mT4t8JflMQxTLFFrSvME /RVb5DZVuXf5PUhFM/KxDsDTI7Nzwb4yqEg3Fz0EC5YS7dS75Hjk/rXCCNXh/lOqFUhI qtTK3KQdAV12PkdO4HgUmBstotegxuqZgHimP3WzxmIE4XyUvvswEv02wrUBg3oXSgCw d6a9qt1VeW+7k+Eavh86NQreFfJ6Dxdo97vvkm8yJ7uQvpnw9/52LTxPXeEeLbNihXx4 FF4LfoAcCJWo5k5+ywyARJc72zmWXlxqjPBOlDtHMc6sTBuGqIxqGKVcUS7XGO5PWYcx S91w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:dkim-signature:arc-authentication-results; bh=L3tB6eLUYtafDO7j3ZVM8Nx5jL7u6d5jnq+ibS+v8TU=; b=mSFJsYMcbXe5mwdp/WRB0PRrpKr+XoroQfVezOJsR2qt6r3YgTTYA+ZmHjtVbXTFZa aHZcAYFMOj0S/uHmaDCnMGixjaIr/2Xi9IMJ+NztA2pJkPooRznGonRGOuK5bIz7ZsLq Em1RpWF9RNrSirM4YbZa7u/ZVyzJc5E2+jdqYSyWBX/4cQMjMXF/Aj0zsh9LAfMtw+ds cz930HtbFc8yAClX6xzf5O546Enc7KoqMR9PwtR/kSAGr1iSruHy3mxQd0R2oXHoQtqw wTRjolxsusdYqknBU+/VNUoCgtOUxhYCGkpOuFOGlZ92VTuZI8KkCZPt0mzHyShaXgyd M49g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=OCJXbnh6; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=OCJXbnh6; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,412,1511827200"; d="scan'208";a="705292071" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v5 0/7] Basic Speculation Control feature support Date: Thu, 25 Jan 2018 16:14:08 +0000 Message-Id: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555799403114446?= X-GMAIL-MSGID: =?utf-8?q?1590581659483213447?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add the basic CPUID and MSR definitions for AMD and Intel, followed by the complete no-brainer: Disable KPTI on Intel CPUs which set the RDCL_NO bit to say that they don't need it, as well as others which are known not to speculate such as old Atoms and even older 32-bit chips. Alan will continue an archæological dig to round up some more entries for that table. Also blacklist the early Intel microcodes for Spectre mitigation features, and add the basic support for indirect_branch_prediction_barrier(). The latter is needed to protect userspace and complete the retpoline-based mitigation. Patches on top of it are being bikeshedded as we speak... v2: Cleanups, add AMD bits for STIBP/SPEC_CTRL. v3: Add more CPUs to the exemption for KPTI and clean that up. Add microcode blacklist (RFC). v4: Roll in 'no speculation' list for CPUs not vulnerable to Spectre. Cosmetic cleanups in microcode blacklist table. v5: Update bad KBL microcode revision, blacklist all new features. Add NSC to no_speculation list. David Woodhouse (7): x86/cpufeatures: Add CPUID_7_EDX CPUID leaf x86/cpufeatures: Add Intel feature bits for Speculation Control x86/cpufeatures: Add AMD feature bits for Speculation Control x86/msr: Add definitions for new speculation control MSRs x86/pti: Do not enable PTI on processors which are not vulnerable to Meltdown x86/cpufeature: Blacklist SPEC_CTRL/PRED_CMD on early Spectre v2 microcodes x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support arch/x86/include/asm/cpufeature.h | 7 +++- arch/x86/include/asm/cpufeatures.h | 15 ++++++-- arch/x86/include/asm/disabled-features.h | 3 +- arch/x86/include/asm/msr-index.h | 12 ++++++ arch/x86/include/asm/nospec-branch.h | 13 +++++++ arch/x86/include/asm/required-features.h | 3 +- arch/x86/kernel/cpu/bugs.c | 7 ++++ arch/x86/kernel/cpu/common.c | 49 +++++++++++++++++++++--- arch/x86/kernel/cpu/intel.c | 66 ++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/scattered.c | 2 - 10 files changed, 163 insertions(+), 14 deletions(-) -- 2.7.4