From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226/fEsVa0+XL9LRl0gTiPP4w2jOM9nU39TCnGsN6HY5SNLpvo3+Sg02jGe5Jl2CFRYkv2xW ARC-Seal: i=1; a=rsa-sha256; t=1516896876; cv=none; d=google.com; s=arc-20160816; b=YfB+Y1CIrztfsAC3TyLgp8eAJtfKm2doSdvF92XCGv49rfOGcjbWLPhQRGAXbFrQdT Yve+klQjuSUWfo8FwUKBEwBvlvxAi9ojfJ5qJE3H845IKfntspKuJz0Fr6KtzLIrZkxh vG/s6v3f5a6w9HliGTnFPYC3d7bhKwYFKXUM1qThc3v83p+o6+s698pzyp0MNXEKz5z+ kbEBMfv98QuQtXDX9GlMZce4qe83GnG3z4gjxd/PJ1eLUPcrkPgCIp8gmDIW0N++xIiP r+yS1ruhexNtVoM0HYl0vaOtyEELkhN2HJLx+hpcc/cYmXRbsqkSqfoGSfscuJ9Mn28s EarQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=p/2/AsPq9Ra/bdpTFeyL59UHg4bc+EYl+gi41YxMZPQ=; b=YMULTxNS7aTQGuJOVPhTtudhiSgPp07V96QBwi3b9BJ2eLbmruwJ4EiFAX2eIqXsLX k4pzmwOmmf7LVsUIQAqZTcz74UFdNj6xE9yWUg5+hJsFM5JgrThrgIjLMTxs3gSTqq5L mq9u+9hyKV5PgOiblGBwzUJ+xBaAbO1Xf85iI01rX4FiAoQn6SB9ReKWUxzVf5qFsYZI HlReoh8NJAIOLaGeUbjU6TI/vXmJYwJ3AHpYXB1DQMnQxGAU5MdA9HqukToFMssPMAlg kYrkvKKR+gotUSTiENT9WeVVOXo9JaX/IuzmsPQX/Exz8D+lEL8XShJROM/OcONa1t7+ dXug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=BUl6kigN; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=BUl6kigN; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,412,1511827200"; d="scan'208";a="705292080" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v5 2/7] x86/cpufeatures: Add Intel feature bits for Speculation Control Date: Thu, 25 Jan 2018 16:14:10 +0000 Message-Id: <1516896855-7642-3-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> References: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555812493666698?= X-GMAIL-MSGID: =?utf-8?q?1590581659319767607?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add three feature bits exposed by new microcode on Intel CPUs for speculation control. Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman Reviewed-by: Borislav Petkov --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7b25cf3..0a51070 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -320,6 +320,9 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation Control (IBRS + IBPB) */ +#define X86_FEATURE_STIBP (18*32+27) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ /* * BUG word(s) -- 2.7.4