From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2259DmyOw+zrJxTMB6QSicHdzjkcggdeHc7aavSg5h3hSiYtyIZZJF1ePsrzMQ7yYGjxntjs ARC-Seal: i=1; a=rsa-sha256; t=1516896880; cv=none; d=google.com; s=arc-20160816; b=VSagmv4rdk5J0piFINOGTyfvWUzIY8DMO68Qm1CtNu49d8g+K9q8L70UhjJD/pbBmn OA8QgjTXDTr02HMg9XxDxudFk6Qny4j2XczjzThIyszvTDZPuKyNroobS34KLsCJ6hcg jKWRUINIZ8DPCQdic4YaT3VbQjcrdL8NgGXZoZV9C1jdWPi6nl7s2OEgattB22MOpZyX aUKe4itTNvNC0ofNryVTjXcF14ZnEW6hTAOhFzGUgP6Y2jWcMOa5xdwL4K0l9uGL0vYh kCMiX65L8rHkoK/hPn2txjEQZgmmNFM1eHp+EIzv3eJKzoDxbJybMfoMNlacCsg/lcQF Fleg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=C4k0L+16qv9f8gu34YJZS5nqCBs+ElTbJMSmTxfZrzg=; b=PttwwneEOLil7H66dvEJmW87FBNqWH+ylATnlM/S2lSd1cSDWFhN+JYi2cDYGgt7Lr DWDJqIv69qs26AJ+VH4OIrWPJaRtQQZ0qYV6tAwZT/4rtjlh2yhAX8qfR2ixZGwLnaPU A61iM6saKqye4P/CN4P72bfL3yK4F0inMZZapYG5SqydLV0TG7jko0zKsc0SwHjwu4vR +L+s5z5oaw9ohDc2/xGA3/L6oj9xWfx98uTvjX0hJBawnCjUNqAlkLFe9Nmuk9WvBQhu Deh2sFZUOBM7M7W9sRkmOpcL/KMfH4TJWz7Na4WLTBpz2LxuF37Cz1L4kLuwglOUl3Ao S2EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=Q8iz5q9b; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=Q8iz5q9b; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,412,1511827200"; d="scan'208";a="705292092" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v5 3/7] x86/cpufeatures: Add AMD feature bits for Speculation Control Date: Thu, 25 Jan 2018 16:14:11 +0000 Message-Id: <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> References: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555819438908618?= X-GMAIL-MSGID: =?utf-8?q?1590581663714870909?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@amd.com Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman --- arch/x86/include/asm/cpufeatures.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 0a51070..ae3212f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -269,6 +269,9 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR (AMD) */ +#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR only (AMD) */ +#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ -- 2.7.4