From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226tgF1YXXmDp8049DlIHFPQkiU8+KQcVfg1gdHRjhN+08/u17Wia/mEhpt4iW/9jPu6Z4kB ARC-Seal: i=1; a=rsa-sha256; t=1516896880; cv=none; d=google.com; s=arc-20160816; b=f1tTb0oppGIE3fxSYXPFQHP6DnmnjZZooO8tP9g0VGqb8T7TbXJA229B7jaeI/K/Bn AVxq9REdzW681D0fTmxzFEbcEOdr2L9b1GYXQQX3fOCsRGe9FkYe6FUtgWbG1GoDzZv/ o8j9TgGsvTyPzLwsvbO5HiEYGGTKjIs7MzeQ+qxH2K2GleA8nLwNsw303uA90A6Zxt8y lkYkR1iXqPzQ0aPPeShHNrT7dx3PrvIr8luZV2GKIDP4JPdJtl++V6aAHXmyXwMUW3H/ MQceVuxYqtRv0W6htGQS2GXrPJLKF5bBXcwqFueoFsnnVQNCoyvKKLa7KZGlHKLgEkIh kLXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:to:from :dkim-signature:arc-authentication-results; bh=GkhjsaMS5Bme/Ox+tx4JKBCYNXZocDfBtlXw8PoahO4=; b=o4Tqj5gWkffC4zBiez0uM0qOvfER/hAi2cxvF1eFIDyp7Vf0WOpSg4qdy338/z29wI foxO6p2ejJYRUOEKj5aWiPSdLM5gwqjbjKwxZ45nkAGu/lDXAUBGUaKoTxtt3AaHgX8r U38UwGKWPsSv+zOhxLuX8AiEZxRMiGnKLVQIfDpzwljpcv7HwesaqR8UJfxTcHDEgBdF nP29ikH0PkB06OUVRd2QXpNVOdeBxIw9uz3oVziqOvKqdgLB5OHN/Sc0Omd+Ty+Sahu1 PGo6yJb7II7S16iZ7ujdoIsFwVUXbcWwccu4raAzFwxKsaXsmQ61j8hSmld2ECJ9yKhs ma0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=cb5BqhsT; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=cb5BqhsT; spf=pass (google.com: domain of prvs=556dd1d58=dwmw@amazon.com designates 72.21.198.25 as permitted sender) smtp.mailfrom=prvs=556dd1d58=dwmw@amazon.com; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk X-IronPort-AV: E=Sophos;i="5.46,412,1511827200"; d="scan'208";a="705292090" From: David Woodhouse To: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: [PATCH v5 4/7] x86/msr: Add definitions for new speculation control MSRs Date: Thu, 25 Jan 2018 16:14:12 +0000 Message-Id: <1516896855-7642-5-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> References: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555835178069748?= X-GMAIL-MSGID: =?utf-8?q?1590581663850415028?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES. See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: David Woodhouse Reviewed-by: Greg Kroah-Hartman --- arch/x86/include/asm/msr-index.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index fa11fb1..eb83ff1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,13 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ + +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ + #define MSR_PPIN_CTL 0x0000004e #define MSR_PPIN 0x0000004f @@ -57,6 +64,11 @@ #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) #define MSR_MTRRcap 0x000000fe + +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ + #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e -- 2.7.4