From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751632AbeA2Qbj (ORCPT ); Mon, 29 Jan 2018 11:31:39 -0500 Received: from mga09.intel.com ([134.134.136.24]:11472 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751322AbeA2Qal (ORCPT ); Mon, 29 Jan 2018 11:30:41 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,431,1511856000"; d="scan'208";a="25629349" From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: acme@kernel.org, tglx@linutronix.de, jolsa@redhat.com, eranian@google.com, ak@linux.intel.com, Kan Liang Subject: [PATCH V3 4/5] perf/x86/intel: fix pmu read for large PEBS Date: Mon, 29 Jan 2018 08:29:32 -0800 Message-Id: <1517243373-355481-5-git-send-email-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517243373-355481-1-git-send-email-kan.liang@linux.intel.com> References: <1517243373-355481-1-git-send-email-kan.liang@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang Large PEBS needs to be specially handled in event count read. It is only available for intel_pmu. Only need to specially handle the large PEBS. For the threshold is one, even auto-reload is enabled, it doesn't need to be specially handled. Because, - auto-reload is only effect when event overflow. Once there is an overflow, the NMI handler will automatically drain_pebs(). - For other cases, x86_perf_event_update() is good enough. Fixes: b8241d20699e ("perf/x86/intel: Implement batched PEBS interrupt handling (large PEBS interrupt threshold)") Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 731153a..1610a9d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2060,6 +2060,14 @@ static void intel_pmu_del_event(struct perf_event *event) intel_pmu_pebs_del(event); } +static void intel_pmu_read_event(struct perf_event *event) +{ + if (intel_pmu_large_pebs_read(event)) + return; + + x86_perf_event_update(event); +} + static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) { int idx = hwc->idx - INTEL_PMC_IDX_FIXED; @@ -3495,6 +3503,7 @@ static __initconst const struct x86_pmu intel_pmu = { .disable = intel_pmu_disable_event, .add = intel_pmu_add_event, .del = intel_pmu_del_event, + .read = intel_pmu_read_event, .hw_config = intel_pmu_hw_config, .schedule_events = x86_schedule_events, .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, -- 2.7.4