From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753121AbeAaMyV (ORCPT ); Wed, 31 Jan 2018 07:54:21 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:60587 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752944AbeAaMyT (ORCPT ); Wed, 31 Jan 2018 07:54:19 -0500 Message-ID: <1517403243.14302.1.camel@pengutronix.de> Subject: Re: [PATCH v3 33/43] drm/panel: simple: Change mode for Sharp lq123p1jx31 From: Lucas Stach To: Thierry Escande , Archit Taneja , Inki Dae , Thierry Reding , Sandy Huang , Sean Paul , David Airlie , Tomasz Figa , Enric Balletbo i Serra Cc: Zain Wang , Lin Huang , Douglas Anderson , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Yakir Yang , =?ISO-8859-1?Q?=D8rjan?= Eide , Mark Yao , Haixia Shi Date: Wed, 31 Jan 2018 13:54:03 +0100 In-Reply-To: <20180130202913.28724-34-thierry.escande@collabora.com> References: <20180130202913.28724-1-thierry.escande@collabora.com> <20180130202913.28724-34-thierry.escande@collabora.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.22.6-1+deb9u1 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2001:67c:670:100:fa0f:41ff:fe58:4010 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande: > From: Sean Paul > > Change the mode for Sharp lq123p1jx31 panel to something more > rockchip-friendly such that we can use the fixed PLLs to > generate the pixel clock This should really switch to a display timing instead of exposing a single mode. The display timing has min, typical, max tuples for all the timings values, which would allow the attached driver to vary the timings inside the allowed bounds if it makes sense. Trying to hit a specific pixel clock to free up a PLL is exactly one of the use cases envisioned for the display timings stuff. Regards, Lucas > Cc: Chris Zhong > Cc: Stéphane Marchesin > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > --- >  drivers/gpu/drm/panel/panel-simple.c | 7 ++++--- >  1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/panel/panel-simple.c > b/drivers/gpu/drm/panel/panel-simple.c > index 5591984a392b..a4a6ea3ca0e6 100644 > --- a/drivers/gpu/drm/panel/panel-simple.c > +++ b/drivers/gpu/drm/panel/panel-simple.c > @@ -1742,17 +1742,18 @@ static const struct panel_desc > sharp_lq101k1ly04 = { >  }; >   >  static const struct drm_display_mode sharp_lq123p1jx31_mode = { > - .clock = 252750, > + .clock = 266667, >   .hdisplay = 2400, >   .hsync_start = 2400 + 48, >   .hsync_end = 2400 + 48 + 32, > - .htotal = 2400 + 48 + 32 + 80, > + .htotal = 2400 + 48 + 32 + 139, >   .vdisplay = 1600, >   .vsync_start = 1600 + 3, >   .vsync_end = 1600 + 3 + 10, > - .vtotal = 1600 + 3 + 10 + 33, > + .vtotal = 1600 + 3 + 10 + 84, >   .vrefresh = 60, >   .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, > + .type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER, >  }; >   >  static const struct panel_desc sharp_lq123p1jx31 = {