From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2264LmInq2pbMIJm8o6G7rJuk2wJ4BpSQBGGARZa1qH6+HY4HDOWmNd4BcWJvtABgBkaQcWh ARC-Seal: i=1; a=rsa-sha256; t=1517999533; cv=none; d=google.com; s=arc-20160816; b=USwLahapKf5yKX/HPiOothLpYk+59AE+rz+VCh0xESj+8vCj1qrQR3mUu2YzauxWgr qomTSqqZPIvlnOYtOxa2SNbYhM9FtwhnF5lA9ZgwpAEgq38pBZRpaFItIJ9VbnA9uP6s eRfbGL7IfmVMNeulOPUdQrl4TajupRMIi3QuqHxtUc9RmI+al+Ag4feN4Zmb3CBUXiCd sKsPTb5wCEu2sh4cfgVADZwQevpoc/pA3ClySzbyTzzcdeL9f6sWnnH9ci33A3d4ROLp dD3ynfXXwDv+fM05xImMzqZV0f3Px1XpwG5eosBGLp0CJqPqtnHcqq6ZTfsuUiqHN7mL r+hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dmarc-filter:dkim-signature:dkim-signature :arc-authentication-results; bh=OIpR3XKjNkemxQoFGPDqpRqrkbO0w+VXodXkT0q1Mrk=; b=XL8QzcLLYB8h7VGR41NWlkWMf2PVPraq8iTmq5rwGVgrkryScOS1zgkLL9+2qGIjg8 EI0LAtpH6BTXHxO9CZ8OS/eVEsU0HlF+jYhfocDrAqFio3zTJuo8K8hn/MJIcb9cGXoE xV/BSarKJ5s7IyZNmIvfj3o1qkBMbQrBQiIs7wAmrnZoEx6oBmdb32cg6nE/KfleoUpq T6x92P09Sn1Txm0eHGJLbznhK7kcozeoBZpBEIFrT3F520CuN+K+8e0riZmV4G3w6ptW S+sFvvrYZGem6RDY4H7NGH1STe5veH9RQ69RbfEouSls0rlt0wj1uxcyEIxBC8UPpoHr Bb4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=gcdO1fmc; dkim=pass header.i=@codeaurora.org header.s=default header.b=gcdO1fmc; spf=pass (google.com: domain of vivek.gautam@codeaurora.org designates 198.145.29.96 as permitted sender) smtp.mailfrom=vivek.gautam@codeaurora.org Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=gcdO1fmc; dkim=pass header.i=@codeaurora.org header.s=default header.b=gcdO1fmc; spf=pass (google.com: domain of vivek.gautam@codeaurora.org designates 198.145.29.96 as permitted sender) smtp.mailfrom=vivek.gautam@codeaurora.org DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 16A7760A06 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, robin.murphy@arm.com, will.deacon@arm.com, robdclark@gmail.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Cc: alex.williamson@redhat.com, gregkh@linuxfoundation.org, airlied@linux.ie, sboyd@codeaurora.org, sricharan@codeaurora.org, m.szyprowski@samsung.com, architt@codeaurora.org, linux-arm-msm@vger.kernel.org, vivek.gautam@codeaurora.org Subject: [PATCH v7 5/6] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Date: Wed, 7 Feb 2018 16:01:21 +0530 Message-Id: <1517999482-17317-6-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517999482-17317-1-git-send-email-vivek.gautam@codeaurora.org> References: <1517999482-17317-1-git-send-email-vivek.gautam@codeaurora.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1591737878253050989?= X-GMAIL-MSGID: =?utf-8?q?1591737878253050989?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: qcom,smmu-v2 is an arm,smmu-v2 implementation with specific clock and power requirements. This smmu core is used with multiple masters on msm8996, viz. mdss, video, etc. Add bindings for the same. Signed-off-by: Vivek Gautam Reviewed-by: Rob Herring --- .../devicetree/bindings/iommu/arm,smmu.txt | 43 ++++++++++++++++++++++ drivers/iommu/arm-smmu.c | 13 +++++++ 2 files changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 8a6ffce12af5..169222ae2706 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,10 +17,19 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,-smmu-v2", "qcom,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. + A number of Qcom SoCs use qcom,smmu-v2 version of the IP. + "qcom,-smmu-v2" represents a soc specific compatible + string that should be present along with the "qcom,smmu-v2" + to facilitate SoC specific clocks/power connections and to + address specific bug fixes. + An example string would be - + "qcom,msm8996-smmu-v2", "qcom,smmu-v2". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -71,6 +80,23 @@ conditions. or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. +- clock-names: Should be "bus", and "iface" for "qcom,smmu-v2" + implementation. + + "bus" clock for "qcom,smmu-v2" is required for downstream + bus access and for the smmu ptw. + + "iface" clock is required to access smmu's registers through + the TCU's programming interface. + +- clocks: Phandles for respective clocks described by clock-names. + +- power-domains: Phandles to SMMU's power domain specifier. This is + required even if SMMU belongs to the master's power + domain, as the SMMU will have to be enabled and + accessed before master gets enabled and linked to its + SMMU. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -137,3 +163,20 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation */ + smmu4: iommu { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c7e924d553bd..721cf1291f85 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -119,6 +119,7 @@ enum arm_smmu_implementation { GENERIC_SMMU, ARM_MMU500, CAVIUM_SMMUV2, + QCOM_SMMUV2, }; struct arm_smmu_s2cr { @@ -1950,6 +1951,17 @@ struct arm_smmu_match_data { ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500); ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2); +static const char * const qcom_smmuv2_clks[] = { + "bus", "iface", +}; + +static const struct arm_smmu_match_data qcom_smmuv2 = { + .version = ARM_SMMU_V2, + .model = QCOM_SMMUV2, + .clks = qcom_smmuv2_clks, + .num_clks = ARRAY_SIZE(qcom_smmuv2_clks), +}; + static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 }, { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 }, @@ -1957,6 +1969,7 @@ struct arm_smmu_match_data { { .compatible = "arm,mmu-401", .data = &arm_mmu401 }, { .compatible = "arm,mmu-500", .data = &arm_mmu500 }, { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 }, + { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation