From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x226+wqmePe42oESghZeQeq+nd/eE/rdqSVEaENjpetkPoAiqC/xxPpqzNoN9LTW8XN3XMBOA ARC-Seal: i=1; a=rsa-sha256; t=1518168359; cv=none; d=google.com; s=arc-20160816; b=o0lWrsS5YTxu3hWhI26c+T0FIzFHPFAteYt+rXtkFsXll1FP3j3COtc9n2269niD+3 tRpcuVE+CwgzPdFzGmL02MoEbwN/JyXYqPsi/DuyJ7MxZpyCLem6Q/DYooiVRvrQYOR4 nRWFhLwZEuoAeeZYYkfH7pbE91BTfOPI9cqQYJvkbRh2VoAx8Y841d8b1c9iBZy8grQs SA/PoMeztNttQBAIGAYRVOGsfixL3ihOzB0GX2IRFJXCYaR0og3vb4A+/uKBLZOCbbkr YxN349J/3F8YXGbkXUZL60X6xJMzixemaHotLfsK9zzmVe8q+Ng/NIus1INB3S0wzmUh 6hbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=cpca8R8tSPFGNg2CkYY+OWUT2oexdUqlX44dCw/JZc8=; b=SK/8SIg00oyTgBriNRHuFsP9MCvoM0QnoW5Tsi2vIU4zdCugxlwYvlMOno9jyNonlo 7BTuNaf8m041g5jsDH5yIebutpwVx4oMsMnCzzb1yTXEu1ivOMOABaV+QzMsVJkZV5i+ 98W3bV5RVxGIgyeaAyFT3x+fVhohrQcDVruhk47m1DqDr6lwbBDPiQIsgJNt4WAki01d Y/vbdm/mXM/JmVYx5Mvhy6RERcnsHu5byJvr+8yzwpjZLuz45AE8GeRJ66BjSWnzPlwN Eju1kdjoMH9S6Wxf495afqM2A13Z2w/mtEa3NDj0HW0Znr27NKg+Et16RqaZ6HLZOkKW 4lHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass (test mode) header.i=@8bytes.org header.s=mail-1 header.b=UXfkV2yj; spf=pass (google.com: domain of joro@8bytes.org designates 2a01:238:4383:600:38bc:a715:4b6d:a889 as permitted sender) smtp.mailfrom=joro@8bytes.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Authentication-Results: mx.google.com; dkim=pass (test mode) header.i=@8bytes.org header.s=mail-1 header.b=UXfkV2yj; spf=pass (google.com: domain of joro@8bytes.org designates 2a01:238:4383:600:38bc:a715:4b6d:a889 as permitted sender) smtp.mailfrom=joro@8bytes.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=8bytes.org From: Joerg Roedel To: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Linus Torvalds , Andy Lutomirski , Dave Hansen , Josh Poimboeuf , Juergen Gross , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , Brian Gerst , David Laight , Denys Vlasenko , Eduardo Valentin , Greg KH , Will Deacon , aliguori@amazon.com, daniel.gruss@iaik.tugraz.at, hughd@google.com, keescook@google.com, Andrea Arcangeli , Waiman Long , Pavel Machek , jroedel@suse.de, joro@8bytes.org Subject: [PATCH 11/31] x86/entry/32: Add PTI cr3 switches to NMI handler code Date: Fri, 9 Feb 2018 10:25:20 +0100 Message-Id: <1518168340-9392-12-git-send-email-joro@8bytes.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518168340-9392-1-git-send-email-joro@8bytes.org> References: <1518168340-9392-1-git-send-email-joro@8bytes.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1591914905960340389?= X-GMAIL-MSGID: =?utf-8?q?1591914905960340389?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Joerg Roedel The NMI handler is special, as it needs to leave with the same cr3 as it was entered with. We need to do this because we could enter the NMI handler from kernel code with user-cr3 already loaded. Signed-off-by: Joerg Roedel --- arch/x86/entry/entry_32.S | 52 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index be1d814..9693485 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -77,6 +77,8 @@ #endif .endm +#define PTI_SWITCH_MASK (1 << PAGE_SHIFT) + /* * User gs save/restore * @@ -167,8 +169,30 @@ .endm -.macro SAVE_ALL_NMI +.macro SAVE_ALL_NMI cr3_reg:req SAVE_ALL + + /* + * Now switch the CR3 when PTI is enabled. + * + * We can enter with either user or kernel cr3, the code will + * store the old cr3 in \cr3_reg and switches to the kernel cr3 + * if necessary. + */ + ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI + + movl %cr3, \cr3_reg + testl $PTI_SWITCH_MASK, \cr3_reg + jz .Lend_\@ /* Already on kernel cr3 */ + + /* On user cr3 - write new kernel cr3 */ + andl $(~PTI_SWITCH_MASK), \cr3_reg + movl \cr3_reg, %cr3 + + /* Restore user cr3 value */ + orl $PTI_SWITCH_MASK, \cr3_reg + +.Lend_\@: .endm /* * This is a sneaky trick to help the unwinder find pt_regs on the stack. The @@ -227,13 +251,29 @@ RESTORE_SKIP_SEGMENTS \pop .endm -.macro RESTORE_ALL_NMI pop=0 +.macro RESTORE_ALL_NMI cr3_reg:req pop=0 /* * Restore segments - might cause exceptions when loading * user-space segments */ RESTORE_SEGMENTS + /* + * Now switch the CR3 when PTI is enabled. + * + * We enter with kernel cr3 and switch the cr3 to the value + * stored on \cr3_reg, which is either a user or a kernel cr3. + */ + ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI + + testl $PTI_SWITCH_MASK, \cr3_reg + jz .Lswitched_\@ + + /* User cr3 in \cr3_reg - write it to hardware cr3 */ + movl \cr3_reg, %cr3 + +.Lswitched_\@: + /* Restore integer registers and unwind stack to iret frame */ RESTORE_INT_REGS RESTORE_SKIP_SEGMENTS \pop @@ -1142,7 +1182,7 @@ ENTRY(nmi) #endif pushl %eax # pt_regs->orig_ax - SAVE_ALL_NMI + SAVE_ALL_NMI cr3_reg=%edi ENCODE_FRAME_POINTER xorl %edx, %edx # zero error code movl %esp, %eax # pt_regs pointer @@ -1170,7 +1210,7 @@ ENTRY(nmi) .Lnmi_return: CHECK_AND_APPLY_ESPFIX - RESTORE_ALL_NMI pop=4 + RESTORE_ALL_NMI cr3_reg=%edi pop=4 jmp .Lirq_return #ifdef CONFIG_X86_ESPFIX32 @@ -1186,12 +1226,12 @@ ENTRY(nmi) pushl 16(%esp) .endr pushl %eax - SAVE_ALL_NMI + SAVE_ALL_NMI cr3_reg=%edi ENCODE_FRAME_POINTER FIXUP_ESPFIX_STACK # %eax == %esp xorl %edx, %edx # zero error code call do_nmi - RESTORE_ALL_NMI + RESTORE_ALL_NMI cr3_reg=%edi lss 12+4(%esp), %esp # back to espfix stack jmp .Lirq_return #endif -- 2.7.4