From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752589AbeBVGeO (ORCPT ); Thu, 22 Feb 2018 01:34:14 -0500 Received: from mga03.intel.com ([134.134.136.65]:55370 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752478AbeBVGde (ORCPT ); Thu, 22 Feb 2018 01:33:34 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,377,1515484800"; d="scan'208";a="31891778" From: Ashok Raj To: bp@suse.de Cc: Ashok Raj , X86 ML , LKML , Thomas Gleixner , Ingo Molnar , Tony Luck , Andi Kleen , Tom Lendacky , Arjan Van De Ven Subject: [v2 2/3] x86/microcode/intel: Perform a cache flush before ucode update. Date: Wed, 21 Feb 2018 22:33:24 -0800 Message-Id: <1519281205-58951-3-git-send-email-ashok.raj@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519281205-58951-1-git-send-email-ashok.raj@intel.com> References: <1519281205-58951-1-git-send-email-ashok.raj@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj Cc: X86 ML Cc: LKML Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Tony Luck Cc: Andi Kleen Cc: Boris Petkov Cc: Tom Lendacky Cc: Arjan Van De Ven --- arch/x86/kernel/cpu/microcode/intel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 137c9f5..50e48c4 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -601,6 +601,13 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) return UCODE_OK; } + /* + * Microcode updates can be safer if the caches are clean. + * Some of the issues around in certain Broadwell parts + * can be addressed by doing a full cache flush. + */ + native_wbinvd(); + /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -817,6 +824,13 @@ static enum ucode_state apply_microcode_intel(int cpu) return UCODE_OK; } + /* + * Microcode updates can be safer if the caches are clean. + * Some of the issues around in certain Broadwell parts + * can be addressed by doing a full cache flush. + */ + wbinvd(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); -- 2.7.4