From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751798AbeBZXEa (ORCPT ); Mon, 26 Feb 2018 18:04:30 -0500 Received: from mail-eopbgr40138.outbound.protection.outlook.com ([40.107.4.138]:19536 "EHLO EUR03-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751608AbeBZXE2 (ORCPT ); Mon, 26 Feb 2018 18:04:28 -0500 From: Marcel Ziswiler To: "digetx@gmail.com" , "linux-tegra@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , "jonathanh@nvidia.com" , "mturquette@baylibre.com" , "pgaikwad@nvidia.com" , "sboyd@kernel.org" , "thierry.reding@gmail.com" , "pdeschrijver@nvidia.com" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH] clk: tegra: fix pllu rate configuration Thread-Topic: [PATCH] clk: tegra: fix pllu rate configuration Thread-Index: AQHTrDGaop9X/jMI1EKf0deimIdiGKO2pjQAgACtrwA= Date: Mon, 26 Feb 2018 23:04:24 +0000 Message-ID: <1519686262.6374.3.camel@toradex.com> References: <20180222230451.15515-1-marcel@ziswiler.com> <31f039e8-9afc-22d1-d478-a7f41db0dace@gmail.com> In-Reply-To: <31f039e8-9afc-22d1-d478-a7f41db0dace@gmail.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=marcel.ziswiler@toradex.com; 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charset="utf-8" Content-ID: <56997F7CFF17FB46BF45C41DA7DCC7B6@eurprd05.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-Network-Message-Id: ff1e0b6a-601b-45a5-b8a9-08d57d6d475f X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Feb 2018 23:04:24.3749 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR05MB340 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w1QN4cNr007419 On Mon, 2018-02-26 at 15:42 +0300, Dmitry Osipenko wrote: > On 23.02.2018 02:04, Marcel Ziswiler wrote: > > Turns out latest upstream U-Boot does not configure/enable pllu > > which > > leaves it at some default rate of 500 kHz: > > > > root@apalis-t30:~# cat /sys/kernel/debug/clk/clk_summary | grep > > pll_u > > pll_u 3 3 0 500000 > > 0 > > > > Of course this won't quite work leading to the following messages: > > > > [ 6.559593] usb 2-1: new full-speed USB device number 2 using > > tegra- > > ehci > > [ 11.759173] usb 2-1: device descriptor read/64, error -110 > > [ 27.119453] usb 2-1: device descriptor read/64, error -110 > > [ 27.389217] usb 2-1: new full-speed USB device number 3 using > > tegra- > > ehci > > [ 32.559454] usb 2-1: device descriptor read/64, error -110 > > [ 47.929777] usb 2-1: device descriptor read/64, error -110 > > [ 48.049658] usb usb2-port1: attempt power cycle > > [ 48.759475] usb 2-1: new full-speed USB device number 4 using > > tegra- > > ehci > > [ 59.349457] usb 2-1: device not accepting address 4, error -110 > > [ 59.509449] usb 2-1: new full-speed USB device number 5 using > > tegra- > > ehci > > [ 70.069457] usb 2-1: device not accepting address 5, error -110 > > [ 70.079721] usb usb2-port1: unable to enumerate USB device > > > > Fix this by actually allowing the rate also being set from within > > the Linux kernel. > > > > Signed-off-by: Marcel Ziswiler > > > > --- > > > > drivers/clk/tegra/clk-pll.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk- > > pll.c > > index 7c369e21c91c..830d1c87fa7c 100644 > > --- a/drivers/clk/tegra/clk-pll.c > > +++ b/drivers/clk/tegra/clk-pll.c > > @@ -1151,6 +1151,8 @@ static const struct clk_ops > > tegra_clk_pllu_ops = { > > .enable = clk_pllu_enable, > > .disable = clk_pll_disable, > > .recalc_rate = clk_pll_recalc_rate, > > + .round_rate = clk_pll_round_rate, > > + .set_rate = clk_pll_set_rate, > > }; > > > > static int _pll_fixed_mdiv(struct tegra_clk_pll_params > > *pll_params, > > > > Tegra's USB PHY driver only enables clock and clk driver doesn't > specify the > clock rate in the init table. Could you please clarify where in the > kernels code > PLL_U rate is getting set? I guess that would be according to the following table isn't it: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree /drivers/clk/tegra/clk-tegra30.c?h=v4.16-rc3#n287