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Wed, 14 Mar 2018 02:08:52 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:45098 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751426AbeCNGIu (ORCPT ); Wed, 14 Mar 2018 02:08:50 -0400 X-UUID: 3c6772111ddc4c5d9b9fca2728f54373-20180314 Message-ID: <1521007723.3717.16.camel@mhfsdcap03> Subject: Re: [PATCH v2 2/3] phy: phy-mtk-tphy: add configurable parameters for slew rate calibrate From: Chunfeng Yun To: Matthias Brugger CC: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Ian Campbell , Ryder Lee , , , , , Date: Wed, 14 Mar 2018 14:08:43 +0800 In-Reply-To: <9abfde61-f81e-1a17-7ff9-85a7017f649b@gmail.com> References: <123d1a24659be168d0b040de4a67612acacf66f1.1520832210.git.chunfeng.yun@mediatek.com> <9abfde61-f81e-1a17-7ff9-85a7017f649b@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.5042-8.2.9001-23718.005 X-TM-AS-Result: No-14.579000-8.000000-10 X-TMASE-MatchedRID: O/y65JfDwwsOwH4pD14DsPHkpkyUphL9dfsypiTqGpue9toQ6h6LEzIl dYjRB7C5yJgT4LTwzDJRUMNmkmV6cHBe8qvb907d5gCHftmwEMJMkOX0UoduuQqiCYa6w8tvGSv JVdW3xMma8V8pK2dHWjxEtja9Tw8PUBXVAm5W8RCeAiCmPx4NwLTrdaH1ZWqC1kTfEkyaZdz6C0 ePs7A07YFInLyeDAoZGgERAt+9nZ6yi1Q6VPsFN4QkqEFWKnpPcRS7s5VhxmzM78CqMVoihQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--14.579000-8.000000 X-TMASE-Version: SMEX-12.5.0.5042-8.2.9001-23718.005 X-TMASE-POSTMAN: 2-d; X-MTK: N Sender: linux-usb-owner@vger.kernel.org X-Mailing-List: linux-usb@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Wed, 2018-03-14 at 00:21 +0100, Matthias Brugger wrote: > > On 03/12/2018 06:25 AM, Chunfeng Yun wrote: > > There are two parameters, ref_clk and coefficient, for U2 slew rate > > calibrate which may vary on different SoCs, here allow them to be > > configurable > > > > Signed-off-by: Chunfeng Yun > > Reviewed-by: Matthias Brugger > Thanks > > > --- > > drivers/phy/mediatek/phy-mtk-tphy.c | 20 +++++++++++++++----- > > 1 file changed, 15 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c > > index 6073c25..38c281b 100644 > > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > > @@ -306,6 +306,8 @@ struct mtk_tphy { > > const struct mtk_phy_pdata *pdata; > > struct mtk_phy_instance **phys; > > int nphys; > > + int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ > > + int src_coef; /* coefficient for slew rate calibrate */ > > }; > > > > static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, > > @@ -360,16 +362,17 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, > > writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); > > > > if (fm_out) { > > - /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ > > - tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; > > - tmp /= fm_out; > > + /* ( 1024 / FM_OUT ) x reference clock frequency x coef */ > > + tmp = tphy->src_ref_clk * tphy->src_coef; > > + tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; > > calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); > > } else { > > /* if FM detection fail, set default value */ > > calibration_val = 4; > > } > > - dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n", > > - instance->index, fm_out, calibration_val); > > + dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", > > + instance->index, fm_out, calibration_val, > > + tphy->src_ref_clk, tphy->src_coef); > > > > /* set HS slew rate */ > > tmp = readl(com + U3P_USBPHYACR5); > > @@ -1041,6 +1044,13 @@ static int mtk_tphy_probe(struct platform_device *pdev) > > tphy->u3phya_ref = NULL; > > } > > > > + tphy->src_ref_clk = U3P_REF_CLK; > > + tphy->src_coef = U3P_SLEW_RATE_COEF; > > + /* update parameters of slew rate calibrate if exist */ > > + device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", > > + &tphy->src_ref_clk); > > + device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef); > > + > > port = 0; > > for_each_child_of_node(np, child_np) { > > struct mtk_phy_instance *instance; > >