From: "David S. Miller" <davem@redhat.com>
To: NIIBE Yutaka <gniibe@m17n.org>
Cc: linux-kernel@vger.kernel.org
Subject: Re: The interface of flush_cache_page
Date: Sat, 4 Aug 2001 02:48:02 -0700 (PDT) [thread overview]
Message-ID: <15211.50386.927163.766367@pizda.ninka.net> (raw)
In-Reply-To: <200108040610.f746AlJ19336@mule.m17n.org>
In-Reply-To: <200108040610.f746AlJ19336@mule.m17n.org>
NIIBE Yutaka writes:
> When it is called from vmscan.c:try_to_swap_out, as the PTE is cleared
> to be zero, we have no way to know what phisical address to match.
That is really an error, and it is only because the last time the
logic try_to_swap_out() logic got rearranges the cache flush got moved
lower down.
In fact, several architectures will take a fatal trap due to
this sequence. On these systems the tlb must be able to translate the
virtual address given to it for the flush, and that translation must
be valid.
Thus, the code there should be:
flush_cache_page(vma, address);
pte = ptep_get_and_clear(page_table);
flush_tlb_page(vma, address);
And the flush_cache_page() further down in that function then can be
removed.
Feel free to send this fix to Linus. It is probably causing
HyperSparc sparc32 to fail to work at all once a swap happens,
if platforms using that chip work at all.
Later,
David S. Miller
davem@redhat.com
next prev parent reply other threads:[~2001-08-04 9:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-08-04 6:10 NIIBE Yutaka
2001-08-04 9:48 ` David S. Miller [this message]
2001-08-04 10:44 ` NIIBE Yutaka
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