From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AIpwx48UhKIR6Kyo15zsKMs42Q5joIfK49xw9UoLJP74a5k5Esg2FFAysU0GCAR9s2ICLMKwP2K7 ARC-Seal: i=1; a=rsa-sha256; t=1523892348; cv=none; d=google.com; s=arc-20160816; b=Po5GSwS5fVsjuF7zRw44VwqqUATn+LosO9uhZdxyNBBHY8YvkuxP+y94QLZEtIrv12 ca/ExEBgtZg3tMg3nZjzL7u2oO33U9ASv80x//Cp9G5L9KyyAd4GWbEjsb4cNiPypBvQ Ep64CH4LvyGWYKQOtfoMRj9cAP2MywngT5HKoIZcFhrdcOKKcjrLpf3qk0VzjaUaYLgW 0s715PCKrK9v7Cp9tbipd3rVj26GpyXM9oWh8URLoS9tibjGfCz1x/m0oNpaa9I2goTE cYkKIQKO5c4I2J2Augb3J+cqz0mxG9xJgxlyD1kRXdko0F54IXEUYGSRIi0uco93lwqg ETXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=WeXc/Ao+LnCoDUTx4VGRj1iHDitMElHV+QHmbKrVox4=; b=h9g2nicH8OiWS/3yzEhkh8AlxEdnVBtOKxFm7n7Lf7ZDH6hyWNehq440wxZ0ce79h8 ytIVVzrpqB+7aOnS1vYXTvhn3eewh5ujGkKAYBi9DtA8apPxq4Swi8r3pYupC6WUHDMY N1sSvZ5CL+Z6aBZOufxlUWdfLaImRALrPclUCaJ99mLLaAt/fPtQGxyIy1cPK8qbZN+e 73wwcF/FaJ0uP8GPi/oI/9JgSLGN2bdWfchGxprEqE0zmJNhSKqqvBroi+O8oK/KJWdy sIg5MNYk4lDluSRt8JTN7x+i2F7Ajc3lTMY2jCRdi0DumJiUZaOi2rXW5faOdySEAx4z KTmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass (test mode) header.i=@8bytes.org header.s=mail-1 header.b=izzdsz4s; spf=pass (google.com: domain of joro@8bytes.org designates 81.169.241.247 as permitted sender) smtp.mailfrom=joro@8bytes.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Authentication-Results: mx.google.com; dkim=pass (test mode) header.i=@8bytes.org header.s=mail-1 header.b=izzdsz4s; spf=pass (google.com: domain of joro@8bytes.org designates 81.169.241.247 as permitted sender) smtp.mailfrom=joro@8bytes.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=8bytes.org From: Joerg Roedel To: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Linus Torvalds , Andy Lutomirski , Dave Hansen , Josh Poimboeuf , Juergen Gross , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , Brian Gerst , David Laight , Denys Vlasenko , Eduardo Valentin , Greg KH , Will Deacon , aliguori@amazon.com, daniel.gruss@iaik.tugraz.at, hughd@google.com, keescook@google.com, Andrea Arcangeli , Waiman Long , Pavel Machek , "David H . Gutteridge" , jroedel@suse.de, joro@8bytes.org Subject: [PATCH 21/35] x86/mm/pae: Populate valid user PGD entries Date: Mon, 16 Apr 2018 17:25:09 +0200 Message-Id: <1523892323-14741-22-git-send-email-joro@8bytes.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523892323-14741-1-git-send-email-joro@8bytes.org> References: <1523892323-14741-1-git-send-email-joro@8bytes.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1597916942795572076?= X-GMAIL-MSGID: =?utf-8?q?1597916942795572076?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Joerg Roedel Generic page-table code populates all non-leaf entries with _KERNPG_TABLE bits set. This is fine for all paging modes except PAE. In PAE mode only a subset of the bits is allowed to be set. Make sure we only set allowed bits by masking out the reserved bits. Signed-off-by: Joerg Roedel --- arch/x86/include/asm/pgtable_types.h | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 1e5a406..65f2dbaf 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -50,6 +50,7 @@ #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL) #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1) #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2) +#define _PAGE_SOFTW3 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW3) #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT) #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL) @@ -267,14 +268,37 @@ typedef struct pgprot { pgprotval_t pgprot; } pgprot_t; typedef struct { pgdval_t pgd; } pgd_t; +#ifdef CONFIG_X86_PAE + +/* + * PHYSICAL_PAGE_MASK might be non-constant when SME is compiled in, so we can't + * use it here. + */ + +#define PGD_PAE_PAGE_MASK ((signed long)PAGE_MASK) +#define PGD_PAE_PHYS_MASK (((1ULL << __PHYSICAL_MASK_SHIFT)-1) & PGD_PAE_PAGE_MASK) + +/* + * PAE allows Base Address, P, PWT, PCD and AVL bits to be set in PGD entries. + * All other bits are Reserved MBZ + */ +#define PGD_ALLOWED_BITS (PGD_PAE_PHYS_MASK | _PAGE_PRESENT | \ + _PAGE_PWT | _PAGE_PCD | \ + _PAGE_SOFTW1 | _PAGE_SOFTW2 | _PAGE_SOFTW3 ) + +#else +/* No need to mask any bits for !PAE */ +#define PGD_ALLOWED_BITS (~0ULL) +#endif + static inline pgd_t native_make_pgd(pgdval_t val) { - return (pgd_t) { val }; + return (pgd_t) { val & PGD_ALLOWED_BITS }; } static inline pgdval_t native_pgd_val(pgd_t pgd) { - return pgd.pgd; + return pgd.pgd & PGD_ALLOWED_BITS; } static inline pgdval_t pgd_flags(pgd_t pgd) -- 2.7.4