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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1f296c66sm100369966b.109.2024.10.25.12.40.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Oct 2024 12:40:39 -0700 (PDT) Message-ID: <15238992-4ede-4b85-9947-391baaa4c8a9@oss.qualcomm.com> Date: Fri, 25 Oct 2024 21:40:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] arm64: dts: qcom: qcs615: Add QUPv3 configuration To: Viken Dadhaniya , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_msavaliy@quicinc.com, quic_anupkulk@quicinc.com References: <20241011103346.22925-1-quic_vdadhani@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241011103346.22925-1-quic_vdadhani@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: WGZEWb5Hylp4xRJOfoUKHGpxVlf0Etvx X-Proofpoint-ORIG-GUID: WGZEWb5Hylp4xRJOfoUKHGpxVlf0Etvx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 suspectscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250150 On 11.10.2024 12:33 PM, Viken Dadhaniya wrote: > Add DT support for QUPv3 Serial Engines. > > Co-developed-by: Mukesh Kumar Savaliya > Signed-off-by: Mukesh Kumar Savaliya > Signed-off-by: Viken Dadhaniya > --- [...] > + qup_opp_table: opp-table-qup { > + compatible = "operating-points-v2"; opp-shared; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > @@ -392,6 +427,24 @@ > #size-cells = <1>; > }; > > + gpi_dma0: qcom,gpi-dma@800000 { > + compatible = "qcom,sdm845-gpi-dma"; You must define a new compatible for qcs615, sdm845 is used as a fallback (so that we don't have to add new driver entries). You will however need to submit a separate dt-bindings change. > + reg = <0x0 0x800000 0x0 0x60000>; > + #dma-cells = <3>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <8>; > + dma-channel-mask = <0xf>; > + iommus = <&apps_smmu 0xd6 0x0>; > + status = "disabled"; Any reason? > + }; > + > qupv3_id_0: geniqup@8c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x0 0x8c0000 0x0 0x6000>; > @@ -400,6 +453,7 @@ > <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > clock-names = "m-ahb", > "s-ahb"; > + iommus = <&apps_smmu 0xc3 0x0>; This looks like a separate fix > #address-cells = <2>; > #size-cells = <2>; > status = "disabled"; > @@ -412,13 +466,377 @@ > pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; > pinctrl-names = "default"; > interrupts = ; > - interconnects = <&aggre1_noc MASTER_QUP_0 0 > - &mc_virt SLAVE_EBI1 0>, > - <&gem_noc MASTER_APPSS_PROC 0 > - &config_noc SLAVE_QUP_0 0>; > + interconnects = <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; Why? Also, please use QCOM_ICC_TAG_ALWAYS instead of zeroes Konrad