From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AB8JxZoRxZyspJzuSdQ54h3/eqgmnycu5vbRNzPxslpkD8d9rvsECvi7RTHg2yyh1aM+9c1WW57i ARC-Seal: i=1; a=rsa-sha256; t=1525074113; cv=none; d=google.com; s=arc-20160816; b=0YGVDXMIwuz7oFfvbQAf4LK7tUL7Pl9rj2EeGUxycbVCkvdyOJogMDjO4b05wAdjBs HHLw1ShN6v4/A/TpzSfHlP2JQ9WYWQjZVE+6YkwRxS5yNDhDGoFLoeawlxKm3rwNPbaC GCjCAlc5kv+xyP4rlmtKIYGrm0KivnLTJLna3mSc/ADHIngyDA49DYO6ypNksea+WgWD NodlB6Ft8I/jkYdvoGjhqkoWR7H5KOROCdBaUAiE9Puq8dVEwE3bo8gOp7t/5XyjNJRq NYKyYxK+RaYx2xpEX1C5zTu23PE7v5mHshaC7xfX3OX/DO/etdxhemFGnPFLKZpXc/hm AbJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:dmarc-filter:dkim-signature :dkim-signature:arc-authentication-results; bh=zC7wYI53Msp17k6C+Oni/3sEJikOTcLB1dOkbARmy6o=; b=txwJ9x4VMS+35hQCEbC+Rw8uLOarZEexr6V1c3TnIFlEiLSAzrCnBD8YfB6HymatqG 0mQMuu2b6PBDRGrFskZwTb2YkmqcMIGRBw/jMnXoyI3RyxUSVRsApmsrFHMkdu0r2mZK eBvcZ7RO52A2VXsmEtnunmvVHZTfwbJ4kOEHeVIF6+hkPGvXvBaXGYJZWXC91SKZL33j BJg/hYlifi78siKnK7hWICb43Gj7tiJNelpw+V8WVLvdb7OOZWHvA/YlpJC44Eownp35 EgkzTrM/w1P/rpvi3ZiKMqyDDTepbEhWgpXqRbHpg8MGloSlbzvnacmRgMIbCIUk6ja8 dMjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=HY0X5nKV; dkim=pass header.i=@codeaurora.org header.s=default header.b=JN3rJjSn; spf=pass (google.com: domain of cpandya@codeaurora.org designates 198.145.29.96 as permitted sender) smtp.mailfrom=cpandya@codeaurora.org Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=HY0X5nKV; dkim=pass header.i=@codeaurora.org header.s=default header.b=JN3rJjSn; spf=pass (google.com: domain of cpandya@codeaurora.org designates 198.145.29.96 as permitted sender) smtp.mailfrom=cpandya@codeaurora.org DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7DEB360271 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cpandya@codeaurora.org From: Chintan Pandya To: Will Deacon , Arnd Bergmann , Mark Rutland , Ard Biesheuvel , Marc Zyngier , Andrew Morton Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Philip Elcan , James Morse , Kristina Martsenko , Toshi Kani , Dave Hansen , Vitaly Kuznetsov , Joerg Roedel , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, Chintan Pandya Subject: [PATCH v9 0/4] Fix issues with huge mapping in ioremap for ARM64 Date: Mon, 30 Apr 2018 13:11:30 +0530 Message-Id: <1525074094-25839-1-git-send-email-cpandya@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1599156113340520325?= X-GMAIL-MSGID: =?utf-8?q?1599156113340520325?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: This series of patches takes Toshi Kani 's patches ("fix memory leak/panic in ioremap huge pages") as base and re-bring huge_vmap back for arm64. This series of patches are tested on 4.16 kernel with Cortex-A75 based SoC. The test used for verifying these patches is a stress test on ioremap/unmap which tries to re-use same io-address but changes size of mapping randomly i.e. 4K to 2M to 16K etc. The same test used to reproduce 3rd level translation fault without these fixes (and also of course with Revert "arm64: Enforce BBM for huge IO/VMAP mappings" being part of the tree). These patches can also go into '-stable' branch (if accepted) for 4.6 onwards. >>From V8->V9: - Used __TLBI_VADDR macros in new TLB flush API >>From V7->V8: - Properly fixed compilation issue in x86 file >>From V6->V7: - Fixed compilation issue in x86 case - V6 patches were not properly enumarated >>From V5->V6: - Use __flush_tlb_kernel_pgtable() for both PUD and PMD. Remove "bool tlb_inv" based variance as it is not need now - Re-naming for consistency >>From V4->V5: - Add new API __flush_tlb_kernel_pgtable(unsigned long addr) for kernel addresses >>From V3->V4: - Add header for 'addr' in x86 implementation - Re-order pmd/pud clear and table free - Avoid redundant TLB invalidatation in one perticular case >>From V2->V3: - Use the exisiting page table free interface to do arm64 specific things >>From V1->V2: - Rebased my patches on top of "[PATCH v2 1/2] mm/vmalloc: Add interfaces to free unmapped page table" - Honored BBM for ARM64 Chintan Pandya (4): ioremap: Update pgtable free interfaces with addr arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable arm64: Implement page table free interfaces Revert "arm64: Enforce BBM for huge IO/VMAP mappings" arch/arm64/include/asm/tlbflush.h | 6 ++++++ arch/arm64/mm/mmu.c | 37 +++++++++++++++++++++++++------------ arch/x86/mm/pgtable.c | 8 +++++--- include/asm-generic/pgtable.h | 8 ++++---- lib/ioremap.c | 4 ++-- 5 files changed, 42 insertions(+), 21 deletions(-) -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project